User:SHJX/sandbox

SKU	Launch	GPU Die	Transistors (billion)	Die size	Core		SM count	Cache		Fillrate^[a]^[b]		Memory					Processing power (TFLOPS)							Interface	TDP
					Config^[c]	Clock (MHz)^[d]		L1	L2	Pixel (Gpx/s)	Texture (Gtex/s)	Type	Size	Clock (Gb/s)	Band- width (GB/s)	Bus width	FP6/FP8 Tensor	INT8 Tensor	FP16/BF16 Tensor	TF32 Tensor	FP32	FP64	FP64 Tensor
					Config^[c]	Clock (MHz)^[d]		L1	L2	Pixel (Gpx/s)	Texture (Gtex/s)	Type	Size	Clock (Gb/s)	Band- width (GB/s)	Bus width	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]
H100 CNX	Mar 21, 2023	GH100	80	814 mm²	14,592 456:24:456	690 1845	114	28.5 MB	50 MB			HBM2e	80 GB	3.2	2,039	5120-bit								PCIe 5.0 x16	350 W
H100 PCIe 80GB	Mar 21, 2023				14,592 456:24:456	1095 1755	114	28.5 MB	50 MB			HBM2e		3.2	2,039	5120-bit									350 W
H100 PCIe 96GB	Mar 21, 2023				16,896 528:24:528	1665 1837	132	33 MB	50 MB			HBM3			1,681	5120-bit									700 W
H100 SXM5 64GB	Mar 21, 2023				16,896 528:24:528	1665 1920	132	33 MB	50 MB			HBM3	64 GB		1,008	3072-bit								SXM5	350 W
H100 SXM5 80GB	Mar 21, 2023				16,896 528:24:528	1590 1980	132	33 MB	50 MB			HBM3	80 GB		1,681	5120-bit									350 W
H100 SXM5 96GB	Mar 21, 2023				16,896 528:24:528	1665 1837	132	33 MB	50 MB			HBM3	96 GB	5.3	1,681	5120-bit									350 W
H200 SXM5	Nov 13, 2023				16,896 528:24:528		132	33 MB	50 MB			HBM3e	141 GB		4,915.2	6144-bit	? [3,958]	? [3,958]	? [1,979]	? [989]	67 ?	34 ?	67 ?		700 W
H800 PCIe 80GB	Mar 21, 2023				16,896 528:24:528	1095 1755	132	33 MB	50 MB			HBM2e	80 GB	5.3	2,039	5120-bit								PCIe 5.0 x16	350 W
H800 SXM5	Mar 21, 2023				16,896 528:24:528	1095 1755	132	33 MB	50 MB			HBM3	80 GB	5.3	2,039	5120-bit								SXM5	350 W

^ Pixel fillrate is calculated as the number of render output units (ROPs) multiplied by the base (or boost) core clock speed.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^ CUDA Cores
Texture Mapping Units : Render Output Units : Tensor Cores
^ Core boost values (if available) are stated below the base value inside brackets.

SKU	Launch	GPU Die	Transistors (billion)	Die size	Core		Cache		Fillrate^[a]^[b]		Memory					Processing power (TFLOPS)						Interface	TDP
					Config^[c]	Clock (MHz)^[d]	L1	L2	Pixel (Gpx/s)	Texture (Gtex/s)	Type	Size	Clock (Gb/s)	Band- width (GB/s)	Bus width	FP4 Tensor	FP6/FP8 Tensor	INT8 Tensor	FP16/BF16 Tensor	TF32 Tensor	FP64 Tensor
					Config^[c]	Clock (MHz)^[d]	L1	L2	Pixel (Gpx/s)	Texture (Gtex/s)	Type	Size	Clock (Gb/s)	Band- width (GB/s)	Bus width	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]	Dense [Sparse]
B100 PCIe 192GB	Mar 21, 2024	GB100	208	mm²	24,576 768:384:768	690 1845	MB	MB			HBM3e	192 GB		8,192	5120-bit	7,000 [14,000]	3,500 [7,000]		1,800 [3,500]	900 [1,800]	30 [-]	PCIe 6.0 x16	700 W
B100 SMX5 192GB	Mar 21, 2024	GB100	208	mm²	24,576 768:384:768	690 1845	MB	MB			HBM3e	192 GB		8,192	5120-bit							SXM5	700 W
B200 PCIe 288GB	Mar 21, 2024	GB100	208	mm²	24,576 768:384:768	690 1845	MB	MB			HBM3e	288 GB	8.0	8,192	5120-bit							PCIe 6.0 x16	1,000 W
B200 SMX5 288GB	Mar 21, 2024	GB100	208	mm²	24,576 768:384:768	690 1845	MB	MB			HBM3e	288 GB	8.0	8,192	5120-bit							SXM5	1,000 W

^ Pixel fillrate is calculated as the number of render output units (ROPs) multiplied by the base (or boost) core clock speed.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed.
^ CUDA Cores
Texture Mapping Units : Render Output Units : Tensor Cores
^ Core boost values (if available) are stated below the base value inside brackets.