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DIRECT FOURIER CONVERSION

Software Defined Radios (SDR) typically use a Digital Down Conversion (DDC) architecture for receivers and Digital Up Conversion architecture (DUC) for transmitters.

DDC takes data from an Analog-to-digital_converter (ADC), applies frequency translation then filters and decimates the data to provide a lower sample rate signal. The DDC process is usually done in a Field-programmable_gate_array (FPGA) or Application-specific_integrated_circuit (ASIC).

The filtered and decimated data stream can then be processed by a Digital_signal_processor (DSP) chip, microprocessor or, via a suitable communications interface, a Personal Computer.

The processes involved in a DDC are as follows:

1. Frequency translation

In this process samples from the ADC are translated (i.e. mixed) to baseband, using a complex sinusoid, such that the lowest frequency of interest is translated to 0Hz. The real data from the ADC is typically multiplied with a complex oscillator in order to created a complex output referred to as the I (inphase) and Q (quadrature) signals. A CORDIC stage is frequently utilised since the one stage can provide the complex oscillator and multiplication.

2. Filter

The required frequency band is then low-pass filtered. In an FPGA or ASIC the initial filtering is frequently provided by one or more CIC filters. This does not require multipliers which may have limited numbers available in small FPGAs. Since the CIC filter has a Sinc_function (sinx/x) shape then typically a final compensating FIR filter will be applied to compensate for the passband droop of the CIC filter(s)

3. Decimation

This reduces the sample rate of the output I & Q signals to a rate appropriate to the filtered bandwidth. Decimation is achieved by discarding samples in the appropriate sequence. Decimation is frequently incorporated in the CIC filters and by the use of Polyphase FIR filters.

All of these processes are processed in the (sampled) time domain.

Where multiple, independent, receivers are required to be generated from a single ADC then the multiple DDCs can be configured to process the ADC data in parallel.

Where large numbers of receivers are required, in the order of many hundreds (perhaps simultaneously accessed via the Internet from remote locations), then the size of FPGA or ASIC required to support this number of receivers can be cost prohibitive.

In which case an alternative architecture can be employed that provides a more cost effective solution. Whilst not a new architecture, since it was first proposed in the late 70's , the current availabilty of high performace PCs and Single Board Computers means the architecure is now cost effective.

Since the prior literature does not use a common term for this architecture the term "Direct Fourier Conversion" (DFC) is proposed.

The DFC architecture uses the frequency domain for the implementation of DDC. The benefits, in terms of reduced CPU requirements, are well documented in relation to the implementation of FIR filters in the frequency domain. Here, the (FFT) of the time series data to be filtered is multiplied by the FFT of the FIR filter coefficients. After multiplication the Inverse FFT (IFFT) is performed to return the filtered signal to the (sampled) time domain.

In terms of CPU load then processing the FFT and IFFT represent the largest loads. In which case it is prudent to do as much signal processing as possible in the frequency which is the approach the DFC uses.

Hence once the FFT of the ADC data has been taken then the rest of the DDC process is undertaken in the frequency domain. The steps are as follows:

1. Take the FFT of the ADC data.

Since the data from the ADC will generally not be contiguous, but received in defined blocks, then either the overlap add or overlap save method must be employed before presenting the ADC data to the FFT.

2. Frequency Translation

3. Filter

4. Decimate

5. Take the inverse FFT.

References:

(1) http://www.3db-labs.com/01598092_MultibandFilterbank.pdf