User:RastaKins/sandbox2
Interrupts
[edit]Interrupts on the 8086 are can be either software or hardware-initiated. Interrupts are long calls that also save the processor status. Interrupt routines typically end with a IRET instruction. All interrupts have a 8-bit interrupt number associated with them. This number is used to look up a segment:offset in a 256 element interrupt vector table stored at addresses 0-3FFH. When any type of interrupt is encountered, the processor status is pushed, CS and IP are pushed, and the interrupt number is multiplied by four to index a new execution address which is loaded from the vector table.
There are three types of software interrupt instructions: INT n, INTO, and a single-byte INT 3 used for debugging.
There are two kinds of hardware interrupts: maskable and non-maskable.
Non-maskable interrupts are higher priority than maskable interrupts. They cannot be disabled by interrupt enable. A low to high transition on the NMI pin essentially causes an INT 2 to execute.
Maskable interrupts are enabled and disabled by the STI and CLI instructions respectively. When the INTR is asserted by a hardware device, the 8086 asserts INTA twice, reading an 8-bit interrupt number from the bus. This number is multiplied by four to point to the associated interrupt service routine in the vector table. Maskable interrupts are disabled when INTA is asserted, but are re-enabled upon executing the IRET instruction at the end of the interrupt service routine.[1]
Interrupts
[edit]Hardware interrupts are initiated by asserting the interrupt request (INT) pin. At the next opcode fetch cycle (M1), the interrupt will be acknowledged with the INTA state code. At this time, an instruction is "jammed" (Intel's word) by external hardware on the data bus. This can be a one-byte RST instruction, or if using an Intel 8259, a CALL instruction. Interrupts may be enabled and disabled with EI and DI instructions, respectively. Interrupts are disabled after an INTA; they must be re-enabled explicitly by the interrupt service routine. The 8080 does not support non-maskable interrupts.