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Series

[edit]

The STM32 family consists of ten series of microcontrollers: F7, F4, F3, F2, F1, F0, L4, L1, L0, W.[1] Each STM32 microcontroller series is based upon either a Cortex-M4F, Cortex-M3, Cortex-M0+, or Cortex-M0 ARM processor core. The Cortex-M4F is conceptually a Cortex-M3[2] plus DSP and single-precision floating point instructions.[3]

STM32 F7

[edit]
STM32 F7 Series [4]
General information
Launched2015
DiscontinuedCurrent
Performance
Max. CPU clock rate216 MHz
Architecture and classification
Technology node90 nm
MicroarchitectureARM Cortex-M7F [5]
Instruction setThumb, Thumb-2,
Sat Math, DSP, FPU

The STM32 F7-series is the group of STM32 microcontrollers based on the ARM Cortex-M7F core. The F7-series have DSP and single precision floating point instructions. The F7 is pin-to-pin compatible with the STM32 F4-series and adds higher clock speed, larger RAM, . The summary for this series is:[6][7][8][9][10]

STM32 F4

[edit]
STM32 F4 Series [9]
General information
Launched2011
DiscontinuedCurrent
Performance
Max. CPU clock rate84  to 180 MHz
Architecture and classification
Technology node90 nm
MicroarchitectureARM Cortex-M4F [3]
Instruction setThumb, Thumb-2,
Sat Math, DSP, FPU

The STM32 F4-series is the first group of STM32 microcontrollers based on the ARM Cortex-M4F core. The F4-series is also the first STM32 series to have DSP and floating point instructions. The F4 is pin-to-pin compatible with the STM32 F2-series and adds higher clock speed, 64K CCM static RAM, full duplex I²S, improved real-time clock, and faster ADCs. The summary for this series is:[6][7][8][9][10]

STM32 F3

[edit]
STM32 F3 Series [11]
General information
Launched2012
DiscontinuedCurrent
Performance
Max. CPU clock rate72 MHz
Architecture and classification
MicroarchitectureARM Cortex-M4F [3]
Instruction setThumb, Thumb-2,
Sat Math, DSP, FPU

The STM32 F3-series is the second group of STM32 microcontrollers based on the ARM Cortex-M4F core, and the most recent series from ST. The F3 is almost pin-to-pin compatible with the STM32 F1-series. The summary for this series is:[12][13][11]

  • Core:
  • Memory:
    • Static RAM consists of 16 / 24 / 32 / 40 KB general purpose with hardware parity check, 0 / 8 KB core coupled memory (CCM) with hardware parity check, 64 / 128 bytes battery-backed with tamper-detection erase.
    • Flash consists of 64 / 128 / 256 KB general purpose, 8 KB system boot, and option bytes.
    • Each chip has a factory-programmed 96-bit unique device identifier number.
  • Peripherals:
    • Each F3-series includes various peripherals that vary from line to line.
  • Oscillators consists of internal (8 MHz, 40 kHz), optional external (1 to 32 MHz, 32.768 to 1000 kHz).
  • IC packages: LQFP48, LQFP64, LQFP100, UFBGA100.
  • Operating voltage range is 2.0 to 3.6 volt.

The distinguishing feature for this series is presence of four fast, 12-bit, simultaneous sampling ADCs (multiplexer to over 30 channels), and interestingly, four matched, 8 MHz bandwidth OpAmps with all pins exposed and additionally internal PGA (Programmable Gain Array) network. The exposed pads allow for a range of analogue signal conditioning circuits like band-pass filters, anti-alias filters, charge amplifiers, integrators/differentiators, 'instrumentation' high-gain differential inputs, and other. This eliminates need for external OpAmps for many applications. The built-in two-channel DAC has arbitrary waveform as well as a hardware-generated waveform (sine, triangle, noise etc.) capability. All analogue devices can be completely independent, or partially internally connected, meaning that one can have nearly everything that is needed for an advanced measurement and sensor interfacing system in a single chip.

The four ADCs can be simultaneously sampled making a wide range of precision analogue control equipment possible. It is also possible to use a hardware scheduler for the multiplexer array, allowing good timing accuracy when sampling more than 4 channels, independent of the main processor thread. The sampling and multiplexing trigger can be controlled from a variety of sources including timers and built-in comparators, allowing for irregular sampling intervals where needed.

The op-amps inputs feature 2-to-1 analogue multiplexer, allowing for a total of eight analogue channels to be pre-processed using the op-amp; all the op-amp outputs can be internally connected to ADCs.

STM32 F2

[edit]
STM32 F2 Series [14]
General information
Launched2010
DiscontinuedCurrent
Performance
Max. CPU clock rate120 MHz
Architecture and classification
Technology node90 nm
MicroarchitectureARM Cortex-M3 [2]
Instruction setThumb, Thumb-2,
Saturated Math

The STM32 F2-series of STM32 microcontrollers based on the ARM Cortex-M3 core. It is the most recent and fastest Cortex-M3 series. The F2 is pin-to-pin compatible with the STM32 F4-series. The summary for this series is:[15][14][16]

  • Core:
  • Memory:
    • Static RAM consists of 64 / 96 / 128 KB general purpose, 4 KB battery-backed, 80 bytes battery-backed with tamper-detection erase.
    • Flash consists of 128 / 256 / 512 / 768 / 1024 KB general purpose, 30 KB system boot, 512 bytes one-time programmable (OTP), 16 option bytes.
    • Each chip has a factory-programmed 96-bit unique device identifier number.
  • Peripherals:
    • Common peripherals included in all IC packages are USB 2.0 OTG HS, two CAN 2.0B, one SPI + two SPI or I2S), three I²C, four USART, two UART, SDIO/MMC, twelve 16-bit timers, two 32-bit timers, two watchdog timers, temperature sensor, 16 or 24 channels into three ADCs, two DACs, 51 to 140 GPIOs, sixteen DMA, real-time clock (RTC), cyclic redundancy check (CRC) engine, random number generator (RNG) engine. Larger IC packages add 8/16-bit external memory bus capabilities.
    • The STM32F2x7 models add Ethernet MAC, camera interface, USB 2.0 OTG FS.
    • The STM32F21x models add a cryptographic processor for DES / TDES / AES, and a hash processor for SHA-1 and MD5.
  • Oscillators consists of internal (16 MHz, 32 kHz), optional external (4 to 26 MHz, 32.768 to 1000 kHz).
  • IC packages: WLCSP64, LQFP64, LQFP100, LQFP144, LQFP176, UFBGA176.
  • Operating voltage range is 1.8 to 3.6 volt.

STM32 F1

[edit]
STM32 F1 Series [17]
General information
Launched2007
DiscontinuedCurrent
Performance
Max. CPU clock rate24  to 72 MHz
Architecture and classification
MicroarchitectureARM Cortex-M3 [2]
Instruction setThumb, Thumb-2,
Saturated Math

The STM32 F1-series was the first group of STM32 microcontrollers based on the ARM Cortex-M3 core and considered their mainstream ARM microcontrollers. The F1-series has evolved over time by increasing CPU speed, size of internal memory, variety of peripherals. There are five F1 lines: Connectivity (STM32F105/107), Performance (STM32F103), USB Access (STM32F102), Access (STM32F101), Value (STM32F100). The summary for this series is:[17][18][19]

  • Core:
  • Memory:
    • Static RAM consists of 4 / 6 / 8 / 10 / 16 / 20 / 24 / 32 / 48 / 64 / 80 / 96 KB.
    • Flash consists of 16 / 32 / 64 / 128 / 256 / 384 / 512 / 768 / 1024 KB.
  • Peripherals:
    • Each F1-series includes various peripherals that vary from line to line.
  • IC packages: VFQFPN36, VFQFPN48, LQFP48, WLCSP64, TFBGA64, LQFP64, LQFP100, LFBGA100, LQFP144, LFBGA144.

STM32 F0

[edit]
STM32 F0 Series [20]
General information
Launched2012
DiscontinuedCurrent
Performance
Max. CPU clock rate48 MHz
Architecture and classification
Technology node16 KB to 128 KB
MicroarchitectureARM Cortex-M0 [21]
Instruction setThumb subset,
Thumb-2 subset

The STM32 F0-series are the first group of ARM Cortex-M0 chips in the STM32 family. The summary for this series is:[22][23][24][20]

  • Core:
    • ARM Cortex-M0 core at a maximum clock rate of 48 MHz.
    • Cortex-M0 options include the SysTick Timer.
  • Memory:
    • Static RAM consists of 4 / 8 / 16 / 20 KB general purpose with hardware parity checking.
    • Flash consists of 16 / 32 / 64 / 128 KB general purpose.
    • Each chip has a factory-programmed 96-bit unique device identifier number.
  • Peripherals:
    • Each F0-series includes various peripherals that vary from line to line.
  • Oscillators consists of internal (8 MHz, 40 kHz), optional external (1 to 32 MHz, 32.768 to 1000 kHz).
  • IC packages: TSSOP20, UFQFPN32, LQFP/UFQFN48, LQFP64, LQFP/UFBGA100.
  • Operating voltage range is 2.0 to 3.6 volt with the possibility to go down to 1.65 V.

STM32 L4

[edit]
STM32 L4 Series
General information
Launched2015
DiscontinuedCurrent
Performance
Max. CPU clock rate80  to 80 MHz
Architecture and classification
MicroarchitectureARM Cortex-M4F [3]
Instruction setThumb, Thumb-2,
Sat Math, DSP, FPU

STM32 L1

[edit]
STM32 L1 Series [25]
General information
Launched2010
DiscontinuedCurrent
Performance
Max. CPU clock rate32 MHz
Architecture and classification
Technology node130 nm
MicroarchitectureARM Cortex-M3 [2]
Instruction setThumb, Thumb-2,
Saturated Math

The STM32 L1-series was the first group of STM32 microcontrollers with a primary goal of ultra-low power usage for battery-powered applications. The summary for this series is:[26][27][25][28]

  • Core:
  • Memory:
    • Static RAM consists of 10 / 16 / 32 / 48 / 80 KB general purpose, 80 bytes with tamper-detection erase.
    • Flash consists of 32 / 64 / 128 / 256 / 384 / 512 KB general purpose with ECC, 4 / 8 KB system boot, 32 option bytes, EEPROM consists of 4 / 8 / 12 / 16 KB data storage with ECC.
    • Each chip has a factory-programmed 96-bit unique device identifier number.
  • Peripherals:
    • Common peripherals included in all IC packages are USB 2.0 FS, two SPI, two I²C, three USART, eight 16-bit timers, two watchdog timers, temperature sensor, 16 to 24 channels into one ADC, two DACs, 37 to 83 GPIOs, seven DMA, real-time clock (RTC), cyclic redundancy check (CRC) engine. The STM32FL152 line adds a LCD controller.
  • Oscillators consists of internal (16 MHz, 38 kHz, variable 64 kHz to 4 MHz), optional external (1 to 26 MHz, 32.768 to 1000 kHz).
  • IC packages: UFQFPN48, LQFP48, LQFP64, TFBGA64, LQFP100, UFBGA100.
  • Operating voltage range is 1.65 to 3.6 volt.

STM32 L0

[edit]
STM32 L0 Series [29]
General information
Launched2014
DiscontinuedCurrent
Performance
Max. CPU clock rate32 MHz
Architecture and classification
MicroarchitectureARM Cortex-M0+ [30]
Instruction setThumb subset,
Thumb-2 subset

The STM32 L0-series is the first group of STM32 microcontrollers based on the ARM Cortex-M0+ core. This series targets low power applications. The summary for this series is:[31][29]

  • Core:
    • ARM Cortex-M0+ core at a maximum clock rate of 32 MHz.
    • Debug interface is SWD with breakpoints and watchpoints. JTAG debugging isn't supported.
  • Memory:
    • Static RAM sizes of 8 KB general purpose with hardware parity checking, 20 bytes battery-backed with tamper-detection erase.
    • Flash sizes of 32 or 64 KB general purpose (with ECC).
    • EEPROM sizes of 2 KB (with ECC).
    • ROM which contains of a boot loader with optional reprogramming of the Flash from USART1, USART2, SPI1, SPI2.
    • Each chip has a factory-programmed 96-bit unique device identifier number.
  • Peripherals:
    • two USART, one low-power UART, two I²C, two SPI or one I²S, one full-speed USB (only L0x2 and L0x3 chips).
    • one 12-bit ADC with multiplexer, one 12-bit DAC, two analog comparators, temperature sensor.
    • timers, low-power timers, watchdog timers, 5 V-tolerant GPIOs, real-time clock, DMA controller, CRC engine.
    • capacitive touch sense and 32-bit random number generator (only L0x2 and L0x3 chips), LCD controller (only L0x3 chips), 128-bit AES engine (only L06x chips).
  • Oscillators consists of optional external 1 to 24 MHz crystal or oscillator, optional external 32.768 kHz crystal or ceramic resonator, multiple internal oscillators, and one PLL.
  • IC packages are LQFP48, LQFP64, TFBGA64.
  • Operating voltage range is 1.8 to 3.6 volt, including a programmable brownout detector.

STM32 W

[edit]
STM32 W Series [32]
Performance
Max. CPU clock rate24 MHz
Architecture and classification
MicroarchitectureARM Cortex-M3 [2]
Instruction setThumb, Thumb-2,
Saturated Math

The STM32 W-series of ARM chips primary feature is targeting RF communication applications. The summary for this series is:[32]

  • Core:
    • ARM Cortex-M3 core at a maximum clock rate of 24 MHz.
  • Memory:
    • Static RAM consists of 8 / 16 kB.
    • Flash consists of 64 / 128 / 192 / 256 kB.
  • Peripherals:
    • Each W-series includes various peripherals that vary from line to line.
  • IC packages: VFQFPN40, VFQFPN48, UFQFPN48.

STM32 J

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STMicroelectronics provides a selection of STM32 microcontrollers ready to be used with Java programming language. This special series embeds the required features to execute Java programs. They are based on the existing STM32 F1, F2, F4, F0, L0 families. There are two sets of special part numbers enabled for Java: Production part numbers end in the letter "J", and sample part numbers end in the letter "U".[33][34]

  1. ^ Cite error: The named reference STM32-WebSite was invoked but never defined (see the help page).
  2. ^ a b c d e Cite error: The named reference M3-Spec was invoked but never defined (see the help page).
  3. ^ a b c d Cite error: The named reference M4-Spec was invoked but never defined (see the help page).
  4. ^ STM32 F7 Website; STMicroelectronics.
  5. ^ Cite error: The named reference M7-Spec was invoked but never defined (see the help page).
  6. ^ a b Cite error: The named reference PR-20110921 was invoked but never defined (see the help page).
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  8. ^ a b Cite error: The named reference PR-20130430 was invoked but never defined (see the help page).
  9. ^ a b c STM32 F4 Website; STMicroelectronics.
  10. ^ a b STM32 F4 Marketing Slides; STMicroelectronics.
  11. ^ a b STM32 F3 Website; STMicroelectronics.
  12. ^ Cite error: The named reference PR-20120626 was invoked but never defined (see the help page).
  13. ^ Cite error: The named reference PR-20120911 was invoked but never defined (see the help page).
  14. ^ a b STM32 F2 Website; STMicroelectronics.
  15. ^ Cite error: The named reference PR-20101130 was invoked but never defined (see the help page).
  16. ^ STM32 F2 Marketing Slides; STMicroelectronics.
  17. ^ a b STM32 F1 Website; STMicroelectronics.
  18. ^ <http://www.st.com/web/en/resource/sales_and_marketing/presentation/product_presentation/stm32_marketing_pres.pdf STM32 F1 Marketing Slides; STMicroelectronics.]
  19. ^ Cite error: The named reference PR-20070611 was invoked but never defined (see the help page).
  20. ^ a b STM32 F0 Website; STMicroelectronics.
  21. ^ Cite error: The named reference M0-Spec was invoked but never defined (see the help page).
  22. ^ Cite error: The named reference PR-20120229 was invoked but never defined (see the help page).
  23. ^ Cite error: The named reference PR-20130708 was invoked but never defined (see the help page).
  24. ^ Cite error: The named reference PR-20140116 was invoked but never defined (see the help page).
  25. ^ a b STM32 L1 Website; STMicroelectronics.
  26. ^ Cite error: The named reference PR-20100419 was invoked but never defined (see the help page).
  27. ^ Cite error: The named reference PR-20110302 was invoked but never defined (see the help page).
  28. ^ STM32 L1 Marketing Slides; STMicroelectronics.
  29. ^ a b STM32 L0 Website; STMicroelectronics.
  30. ^ Cite error: The named reference M0+-Spec was invoked but never defined (see the help page).
  31. ^ Cite error: The named reference PR-20140211 was invoked but never defined (see the help page).
  32. ^ a b STM32W Website; STMicroelectronics.
  33. ^ Cite error: The named reference PR-20130121 was invoked but never defined (see the help page).
  34. ^ STM32 J Website; STMicroelectronics.
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