Talk:C-slowing

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This explanation doesnt make sense. 12.219.83.157 11:13, 15 September 2007 (UTC)[reply]

The explanation is mostly correct, but would need more context and more information about how this relates to pipelining. --Petteri Aimonen (talk) 18:52, 6 November 2010 (UTC)[reply]

to me it looks basically like it *is* pipelining, but the usual description of pipelining completely misses out that intermediate registers (latches) are needed to capture the output from one stage in order to pass it as input to the next. any VLSI ASIC or FPGA programmer knws this, any HDL (Verilog / VHDL / Bluespec) progrmmer knows it as so fundamental it is not made enough of a "big deal" if you know what i mean Lkcl (talk) 05:10, 6 August 2025 (UTC)[reply]