Talk:Accumulator (computing)

Massive rework needed

This is bad, really bad.

First of all this article suggests an accumulator processors has one accumulator (which 6502 did). However numerous examples are contrary to this such as

• 6809 has accumulators A and B that could be concatenated to D, 6308 had even more
• 56300 has again 2 large accumulators of extended width
• 96000 also has 2 accumulators that are even wider

With 2 accumulators you need only a single bit in the instruction to indicate what accumulator is to be used. 68000 has a lot of data registers, and those are not called accumulators, so the article should state clearly where the limit is. Seems the limit is around 4 (ARM Piccolo)

SWEET16 has one accumulator and 15 other registers, a wealth closer to 68000.

Next is the link to accumulator-based architecture which goes to PDP-8, specifically the section Legacy_of_accumulator-based_architectures which no longer exists. Is there any reason why this has to be split up?

Also it seems a bit lacking that the multiply-and-accumulate is not mentioned.

All in all an article in need of an overhaul. --22:47, 22 February 2009 (UTC) Amended --21:30, 23 February 2009 (UTC)

Hopefully such an overhaul will also disambiguate further, since the term "accumulator" in programming applies to a variable in which values are accumulated... 63.249.90.205 (talk) 00:55, 25 June 2010 (UTC)

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What is "early"

#Accumulator machines says Almost all early computers were accumulator machines with only the high-performance "supercomputers" having multiple registers. However, the IBM 7070 had three accumulators, the UNIVAC 1107 had 16, the DEC PDP-6 had 16 and, of course, the IBM System/360 had 16 general registers. The 1107, PDP-6, S/360 and their successors were popular in the 1960s and 1970s, and that era was dominated by machines with multiple accumulators. So where is the cutoff for "early"? --Shmuel (Seymour J.) Metz Username:Chatul (talk) 22:54, 25 July 2021 (UTC)

The IBM 702 apparently had two accumulators, A and B, according to page 17 of the preliminary 702 reference manual, althoug the 705 had 1. And the IBM 1401 has, err, umm, zero? I haven't looked at other vendors' decimal machines. Guy Harris (talk) 23:45, 25 July 2021 (UTC)

@Guy Harris:The 705 actually had 16 accumulators, although IBM referred to the smaller ones as Auxiliary Storage Units (ASUs). Of the IBM machines prior to the S/360, only the 702, 705, 7070 and 7080 had multiple accumulators, although there were machines with both an accumulator and a Multiplier-Quotient register, or equivalent.

It was common for character-oriented machines to be storage-to-storage with no accumulator, as in the 1401/1440/1460/1410/7010 and the RCA 301/3301.

Other vendors' decimal machines followed the same pattern; either word with single accumulator or character with no accumulator. --Shmuel (Seymour J.) Metz Username:Chatul (talk) 18:32, 26 July 2021 (UTC)

Notes

References

GE600 notability

See also: Talk:Bit_manipulation_instructions § GExx series

discussion on another page, moving here that it had, in an *accumulator* machine, eight index (address) registers *at all*. in all honesty this may just be a missed feature of historical computers that was "normal", *or* it could be unique, but looking at accumulator-machines like the PIC Microcontroller they are effectively treating memory as registers, so *sort-of* the bits in the instruction are a direct-addressed operand. Lkcl (talk) 11:59, 13 August 2025 (UTC)

The 6x5 instruction included an 18-bit y field and a six-bit tag field, subdivided into a 2-bit t_m (modification type) and a 4-bit t_d (register designator, except for IT); the tag field determined how to use the y field of the instruction. Effectively there were 13 index registers and two immediate (literal) modes.

Most instruction have one explicit operand and one implicit operand. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:26, 13 August 2025 (UTC)

oh goodness me :) ok they were... 13+2+1=16 a 4-bit specifier, all-zeros was a special encoding, I suspect? the manual is *real* complex, hard even for me to understand :) Lkcl (talk) 17:34, 13 August 2025 (UTC)

X0-X7 - I am thinking of those. Lkcl (talk) 17:35, 13 August 2025 (UTC)

How about The GE-600 series are one-accumulator machines, notable for having cascading indirect addressing and being able to use the either half of A, either half of Q, IC, or any of eight dedicated X registers for address modification. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:31, 13 August 2025 (UTC)

So is the one accumulator the 72-bit AQ register? The 625/635 manual calls that the "accumulator", which can be treated as two 36-bit registers, A and Q. Guy Harris (talk) 19:48, 13 August 2025 (UTC)

I would say yes; there are separate instructions for A, Q and AQ. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:17, 14 August 2025 (UTC)

wow wow a tagged architecture. each data looked-up would in essence have been interpreted further by the address-resolving hardware. wow. Lkcl (talk) 17:38, 13 August 2025 (UTC)

i know where I've seen this before: Power ISA Virtual Memory tables. this is exactly the same underlying concept, but just made accessible in userspace. that too was a hardware-level tree-walk. Lkcl (talk) 17:42, 13 August 2025 (UTC)

Not a tagged architecture in the full tagged architecture sense, but indirect address words included a tag that controlled how indirection and indexing was done; some Indirect then Tally modes were used for 6-bit or 9-bit byte addressing, and one caused a trap. The GE 645 added an additional trap tag; this was used by Multics for dynamic linking - the first reference to a symbol would cause a trap to the dynamic linker, which would map the segment containing the symbol into the address space, resolve the symbol, and update the address not to trap.

And the instruction set is fairly straightforward; the one really hairy part is the indirect addressing. Guy Harris (talk) 19:19, 13 August 2025 (UTC)

In a tagged architecture the actual operand contains a tag identifying its type. That's very different from a field in the instruction or indirect word that happens to be called a tag. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:31, 13 August 2025 (UTC)

That's not a tagged architecture, just an architecture with cascaded indirect addressing. Earlier examples include

• RCA Communications Data Processor (CDP)
• RCA 601
• UNIVAC 1107

-- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:31, 13 August 2025 (UTC)

And speaking of tagged architectures - and of Power ISA - the PowerPC/Power ISA processors used in the AS/400 and IBM Power Systems support memory tagging for the benefit of IBM i with some undocumented features (that are, apparently, rather IBM i-specific). See https://www.devever.net/~hl/ppcas and https://www.devever.net/~hl/power9tags#fn1b; memory tags are encoded in the ECC bits of memory by various forms of trickery. See also some non-public IBM documentation at https://wiki.raptorcs.com/w/images/9/95/POWER9_Registers_vol3_version1.2_pub.pdf, https://wiki.raptorcs.com/w/images/4/49/Book1tags.pdf, https://wiki.raptorcs.com/w/images/d/d9/Book2tags.pdf, and https://wiki.raptorcs.com/w/images/f/f6/Book3tags.pdf.

IBM System/38 and the CISC AS/400s were also tagged, but I think back then IBM didn't bother with commodity memory and didn't do the ECC tricks to store the tags. That instruction set was... interesting. The official instruction set of S/38, AS/400, and IBM i is a super-CISCy ISA that's binary-to-binary translated to native machine code and executed; here's the program logic manual for the lower-level OS functions. It was called "(vertical) microcode" for legal reasons, so IBM wouldn't have to license it to third parties; see the books Frank Soltis wrote about AS/400. It's really just native machine code, the same ISA tha the high-level CISCy code is translated into. See https://bitsavers.org/pdf/ibm/system38/GA21-9331-1_System_38_Functional_Reference_Manual_Feb81.pdf for an older version of the high-level code and https://www.ibm.com/docs/en/i/7.6.0?topic=interfaces-i-machine-interface for the current version. Guy Harris (talk) 19:43, 13 August 2025 (UTC)

i'd heard about this and knew it was a "hidden mode" of POWER9 and probably POWER8 systems that users are NOT supposed to know about :) reminds me of "COME FROM" branch instructions... Lkcl (talk) 12:27, 15 August 2025 (UTC)

It dates back to the RS64 processors and POWER4. Guy Harris (talk) 20:39, 15 August 2025 (UTC)

coooool! Lkcl (talk) 12:24, 15 August 2025 (UTC)

Speaking of the quotient register, at least some of the arithmetic and logical operations that could be done on the A register could be done on the Q register, so it's sorta kinda like a two-accumulator machine. Some of them could also be done on the X registers. Guy Harris (talk) 19:10, 13 August 2025 (UTC)

It's common for accumulator machines with a Q registers to have instructions that operate on both, and for accumulator machines with index registers to have index arithmetic instructions. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:31, 13 August 2025 (UTC) -- Revised 12:17, 14 August 2025 (UTC)

The IBM 7090 (and probably other machines in that line) didn't support as many operations on the MQ or index registers as it did on the AC, although it did support some. The GE-600 series seems to have done a better job of "if you can do it with the A register, you can do it with the Q register and, in many cases, even with the X registers" that the 7090, at least. Guy Harris (talk) 00:01, 15 August 2025 (UTC)

The GE600 apparently had a relatively baroque addressing architecture, but I'm unclear of its relevance to the Accumulator article. Accumulator machines fundamentally are ones which omit a register (or memory) designation for one of the two operands of two-operand actions (e.g. Add), since it is always assumed to be "the accumulator". There are many architectural variations for finding the other operand, commonly selecting one of several index/address registers, and/or specifying indirection through an address located in memory.

The GE6xx perhaps had a particularly elaborate variety of operand effective address generation, but that doesn't seem all that special as concerns the Accumulator article. Is there some sort of change to Accumulator (computing) that should be done because of the GE600 operand development details? --R. S. Shaw (talk) 21:19, 13 August 2025 (UTC)

since it is always assumed to be "the accumulator" is not generally true; some accumulator machines have multiple accumulators, with distinct opcodes for each. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:17, 14 August 2025 (UTC)

Notes

References