User contributions for Punpcklbw

23 March 2025

• 03:2603:26, 23 March 2025 diff hist +1,368 NOP (code) →Machine language instructions: Added a couple of more NOPs-with-side-effects for PowerPC, and a NOP for MSP430.

21 March 2025

• 00:0400:04, 21 March 2025 diff hist +724 List of discontinued x86 instructions →Instructions specific to NEC V-series processors: Updated notes on TEST1 instruction and DS3 segment prefix, and added a footnote with a table of NEC-specific 8080-emulation-mode instructions. Also added a table caption.

20 March 2025

• 21:3321:33, 20 March 2025 diff hist +831 X86 SIMD instruction listings Added sticky headers for the MMX/SSE tables as well as the summary, FMA and AMX tables current
• 21:1121:11, 20 March 2025 diff hist +97 m List of discontinued x86 instructions added sticky headers to a few of the longest tables (3dnow, XOP, NEC)
• 10:0010:00, 20 March 2025 diff hist +476 X86 instruction listings Added sticky-headers to some of the longer tables
• 01:5601:56, 20 March 2025 diff hist +1,882 NOP (code) →Machine language instructions: Added NOPs for intel i860, tensilica xtensa and superh SH-5

19 March 2025

• 23:1123:11, 19 March 2025 diff hist +71 m NOP (code) →Machine language instructions: Added some spacers around the Intel and ARM NOPs, moved Alpha/29K down a little bit, and replaced some ' 's with {{nowrap}} to help prevent wrapping on '/' in e.g "z/Architecture"
• 02:0702:07, 19 March 2025 diff hist +1,589 NOP (code) →Machine language instructions: Added IA-64 NOP

16 March 2025

• 21:5621:56, 16 March 2025 diff hist +3,167 NOP (code) →Machine language instructions: Overhauled the ARM NOPs

15 March 2025

• 16:3016:30, 15 March 2025 diff hist +434 NOP (code) →Machine language instructions: Added TRAPF for 68k
• 15:4215:42, 15 March 2025 diff hist +709 CPUID →EAX=C000'0001h: Centaur Feature Information: Added better references for the Zhaoxin PadLock/GMI feature bits
• 10:5310:53, 15 March 2025 diff hist +739 Zhaoxin →Uses: added QNAP TVS-675 current
• 00:0100:01, 15 March 2025 diff hist +1,173 X86-64 →Recent implementations: Added items on SYSRET's handling of SS and x2apic IPIs ordering wrt memory writes

3 March 2025

• 18:0318:03, 3 March 2025 diff hist +14 m CPUID Added ticks to a few long hex-constants in table-captions
• 00:5000:50, 3 March 2025 diff hist +496 List of x86 cryptographic instructions Updated some footnotes on RDSEED/RDRAND zeroing, Key Locker under APX, and modulus for REP MONTMUL2/XMODEXP current
• 00:3300:33, 3 March 2025 diff hist +2,558 List of x86 cryptographic instructions →Intel SHA instructions: Elaborated a bit on the SHA instructions - also added SHA-512 and SM3 instructions

21 February 2025

• 15:0715:07, 21 February 2025 diff hist +3,699 List of x86 cryptographic instructions →Intel AES instructions: Elaborated on the AES instructions

28 January 2025

• 22:3622:36, 28 January 2025 diff hist +52,355 X86 SIMD instruction listings Replaced MMX/SSE tables with a set of more informative tables that are more structured around the way a whole lot of the SSE/AVX/AVX-512 instructions are really extended versions of older MMX/SSE instructions.
• 22:2022:20, 28 January 2025 diff hist 0 X86 SIMD instruction listings Moved F16C subsection from SSE4 section to AVX section (F16C uses the VEX-prefix and has AVX as a prerequisite, and therefore seems more approriate to group with AVX than with SSE4.)
• 22:1622:16, 28 January 2025 diff hist +584 X86 SIMD instruction listings →Summary of SIMD extensions: Added some extra text on SSE (including "MMX+") and SSE4a
• 21:5321:53, 28 January 2025 diff hist +288 User:Punpcklbw/sandbox →Regularly-encoded floating-point SSE/SSE2 instructions, and AVX/AVX-512 extended variants thereof: Pruned a few comments, added some explanatory text about PXOR/XORPS/XORPD-style instruction triplets, elaborated a bit on XORPS register-clear. current
• 21:1521:15, 28 January 2025 diff hist +22 m User:Punpcklbw/sandbox →MMX instructions added with MMX+/SSE/SSE2/SSSE3, and SSE2/AVX/AVX-512 extended variants thereof: added a wikilink for the PSHUFB
• 21:0421:04, 28 January 2025 diff hist +144 User:Punpcklbw/sandbox →Original Pentium MMX instructions, and SSE2/AVX/AVX-512 extended variants thereof: Polish the content a bit, and add some wikilinks.

27 January 2025

• 20:5620:56, 27 January 2025 diff hist +327 X86 instruction listings →x87 floating-point instructions: Updated notes on FYL2X/FYL2XP1 and FSTSW, moved a note on FBLD, also corrected one FPATAN to FPTAN.
• 00:4400:44, 27 January 2025 diff hist +1,555 NOP (code) →Machine language instructions: Added a note on the many Power ISA NOPs that have side effects

26 January 2025

• 20:4720:47, 26 January 2025 diff hist +2,332 Am386 Added a small section on embedded Am386 processors (Am386SC and Am386EM)
• 16:2516:25, 26 January 2025 diff hist +1,283 X86 instruction listings →x87 instructions added in later processors: Elaborated notes on FXSAVE-vs-FXSAVE64 and the out-of-range behavior of FSIN/FCOS/FSINCOS
• 15:1715:17, 26 January 2025 diff hist +330 NOP (code) →Machine language instructions: The official LoongArch documentation designates ANDI rather than ADDI.D as their preferred NOP-opcode

25 January 2025

• 20:1320:13, 25 January 2025 diff hist +31 m Am386 →AM386 SX: Wharton provides a power number for Am386SXLV as well
• 20:0920:09, 25 January 2025 diff hist +58 m Am386 →Am386DX data: Wharton provides watt numbers for the Am486DXLV, and mentions 132-pin PGA as one of its package options
• 19:5219:52, 25 January 2025 diff hist +1,096 Am386 Added Am386DXLV and Am386SXLV
• 15:4915:49, 25 January 2025 diff hist +1,694 Am386 Added Am386SE

24 January 2025

• 21:0121:01, 24 January 2025 diff hist +916 List of x86 manufacturers →x86-processors for embedded designs only: added CAST x86/x87 IP cores (C80186XL, C80187, C387L) current

22 January 2025

• 03:4803:48, 22 January 2025 diff hist +1,468 User:Punpcklbw/sandbox →Regularly-encoded floating-point SSE/SSE2 instructions, and AVX/AVX-512 extended variants thereof: Elaborated on how the AVX-512 VRCP14*/VRSQRT14* instruction differ from the older VRCP*/VRSQRT* instructions
• 03:2003:20, 22 January 2025 diff hist +990 User:Punpcklbw/sandbox →Original Pentium MMX instructions, and SSE2/AVX/AVX-512 extended variants thereof: Elaborated a bit on 128-bit VMOVDQA atomicity
• 02:4202:42, 22 January 2025 diff hist +2,442 m User:Punpcklbw/sandbox →Integer SSE2/4 instructions with 66h prefix, and AVX/AVX-512 extended variants thereof: Added notes on VPINSRD/VPEXTRD with VEX.W=1 in non-64-bit mode

21 January 2025

• 12:5812:58, 21 January 2025 diff hist +3,650 User:Punpcklbw/sandbox →Original Pentium MMX instructions, and SSE2/AVX/AVX-512 extended variants thereof: Corrected description of shift instructions, added a note on a VEX.W=1 VZEROUPPER erratum, added a reference for AVX-SSE performance penalty, and updated several references to use latest Intel/AMD documentation

20 January 2025

• 04:4804:48, 20 January 2025 diff hist +885 CPUID →EAX=2: Cache and TLB Descriptor Information: Descriptor C3h is a 12-way set-associative TLB on most of the processors that use it (Skylake to Comet Lake)
• 03:0303:03, 20 January 2025 diff hist +2,220 CPUID →EAX=1: Processor Info and Feature Bits: Added a note on a CMPXCHG16B feature bit erratum in Pentium 4, added a small table on the layout of MTRRCAP (which provides additional MTRR information), and grayed out the Itanium NX-bit (EDX bit 20)
• 01:5701:57, 20 January 2025 diff hist +198 m X86 instruction listings →Bit manipulation extensions: added some words on instruction availability, and changed wording a little on BEXTR instruction.
• 01:4801:48, 20 January 2025 diff hist +2,061 X86 instruction listings →x87 floating-point instructions: Updated FXTRACT special-cases, added a note on differences between FXSAVE and FXSAVE64, added one more source for FSIN inaccuracy (old 80387 programmer's reference), added a note on FSTPNCE underflow.

19 January 2025

• 23:3523:35, 19 January 2025 diff hist +750 m X86 instruction listings →Added with other cross-vendor extensions: Added a note on a minor MOVBE instruction encoding erratum
• 23:0923:09, 19 January 2025 diff hist +748 X86 instruction listings →Added in P5/P6-class processors: Added a note on RDMSR/RDTSC/RDPMC clearing the top bits of RDX and RAX in 64-bit mode, and added a source for UD1's ModR/M byte differing between different processors.
• 22:3822:38, 19 January 2025 diff hist +948 m X86 instruction listings →Added with 80286: Added some more notes on LAR/LSL, and VERW buffer-flushing

18 January 2025

• 22:3222:32, 18 January 2025 diff hist +346 X86 SIMD instruction listings →Summary of SIMD extensions: Added some low-end cores (Atoms, Bobcat, Jaguar) to "Added In" column and reordered items to better match release order. Also, corrected SSE2 date to 2000.
• 21:2621:26, 18 January 2025 diff hist −36 X86 SIMD instruction listings →FMA3 and FMA4 instructions: Modified the BF16 FMA instruction mnemonics to match latest Intel AV10.2 documentation (361050-003US)

11 January 2025

• 13:0213:02, 11 January 2025 diff hist +1,668 X86-64 →Differences between AMD64 and Intel 64: added VPINSRD/VPEXTRD with VEX.W=1, 0F0D-NOP with register-argument, and old CLFLUSH/SFENCE ordering

2 January 2025

• 12:0112:01, 2 January 2025 diff hist +429 X86-64 →Recent implementations: added notes on differences for RDRAND, serialization of LMSW/INVPCID/MOV CR8, and reordered some items to put the system-programming items together
• 00:4600:46, 2 January 2025 diff hist +648 X86 instruction listings →Added in P5/P6-class processors: added a note on x2apic IPIs being reorderable across older stores on Intel but not AMD CPUs.
• 00:2000:20, 2 January 2025 diff hist −557 X86-64 →Differences between AMD64 and Intel 64: Updated the BSF/BSR item with some information from the latest Intel SDM (rev 086) - also moved the BSF/BSR and LMSLE items down to the "Older implementations" section since they don't apply to the most recent x86-64 implementations