RISC-V instruction listings

The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

RISC-V Integer Instructions

The table below contains a list of the RV Integer Instructions.. The integer instruction set is divided in the base I part of the ISA that comes in a 32 bit RV32 and 64 bit RV64 version and M, B and Zicond extensions. There is also an A extension for atomic instructions and F and D instructions for floating point operations.

RV Integer (pseudo) Instructions

Instruction	Name	Format	Extension	RV64
li	Load Immediate	rd, imm	I
lui	Load Upper Immediate	rd, imm20	I
auipc	Add Upper Immediate to Program Counter	rd, imm20	I
lb	Load Byte	rd, imm12(rs)	I
lh	Load Half	rd, imm12(rs)	I
lw	Load Word	rd, imm12(rs)	I
ld	Load Double	rd, imm12(rs)	I	x
lbu	Load Byte (U)	rd, imm12(rs)	I
lhu	Load Half (U)	rd, imm12(rs)	I
lwu	Load Word (U)	rd, imm12(rs)	I	x
sb	Store Byte	rs1, imm12(rs2)	I
sh	Store Half	rs1, imm12(rs2)	I
sw	Store Word	rs1, imm12(rs2)	I
sd	Store Double	rs1, imm12(rs2)	I	x
mv	MoVe	rd, rs	I
sext.b	Sign EXTend from first Byte	rd, rs	B
sext.h	Sign Extend from first Half	rd, rs	B
sext.w	Sign EXTend from first Word	rd, rs	I	x
zext.b	Zero EXTend from first Byte	rd, rs	I
zext.h	Zero EXTend from first Half	rd, rs	B
zext.w	Zero EXTend from first Word	rd, rs	B	x
rev8	REVerse byte order	rd, rs	B
czero.eqz	move Conditional on EQual to Zero or ZERO	rd, rs1, rs2	Zicond
czero.nez	move Conditional on Not Equal to Zero or ZERO	rd, rs1, rs2	Zicond
addi	ADD Immediate	rd, rs, imm12	I
add	ADD	rd, rs1, rs2	I
sub	SUBtract	rd, rs1, rs2	I
neg	NEGative.	rd, rs	I
sh1add	SHift1 ADD	rd, rs1, rs2	B
sh2add	SHift2 ADD	rd, rs1, rs2	B
sh3add	SHift3 ADD	rd, rs1, rs2	B
addiw	ADD Word to Word Immediate	rd, rs, imm12	I	x
addw	ADD Word	rd, rs1, rs2	I	x
subw	SUBtract Word	rd, rs1, rs2	I	x
negw	Negative Word	rd, rs	I	x
add.wu	ADD Word(U to double)	rd, rs1, rs2	B	x
sh1add.wu	SHift1 Word(U in double) Add to double	rd, rs1, rs2	B	x
sh2add.wu	SHift2 Word(U in double) Add to double	rd, rs1, rs2	B	x
sh3add.wu	SHift3 Word(U in double) Add to double	rd, rs1, rs2	B	x
mul	MULtiply	rd, rs1, rs2	M
mulh	MULtiply High part	rd, rs1, rs2	M
mulhu	MULtiply High Part Unsigned	rd, rs1, rs2	M
mulhsu	MULtiply High Part Unsigned Signed	rd, rs1, rs2	M
div	DIVide	rd, rs1, rs2	M
divu	DIVide (U)	rd, rs1, rs2	M
rem	REMainder	rd, rs1, rs2	M
remu	REMainder (U)	rd, rs1, rs2	M
mulw	MULtiply Word	rd, rs1, rs2	M	x
min	MINimum	rd, rs1, rs2	B
max	MAXimum	rd, rs1, rs2	B
minu	MINimum (U)	rd, rs1, rs2	B
maxu	MAXimum (U)	rd, rs1, rs2	B
slti	Set Less Than Immediate	rd, rs, imm12	I
sltiu	Set Less Than Immediate (U)	rd, rs, imm12	I
bexti	Bit Extract Immediate	rd, imm5/6	B
seqz	Set EQual to Zero	rd, rs	I
snez	Set Not Equal to Zero	rd, rs	I
slt	Set Less Than	rd, rs1, rs2	I
sltu	Set Less Than (U)	rd, rs1, rs2	I
bext	Bit Extract	rd, rs	B
andi	AND Immediate	rd, rs, imm12	I
ori	OR Immediate	rd, rs, imm12	I
xori	XOR Immediate	rd, rs, imm12	I
bclri	Bit CLeaR Immediate	rd, imm5/6	B
bseti	Bit SET Immediate	rd, imm5/6	B
binvi	Bit INVert Immediate	rd, imm5/6	B
and	AND	rd, rs1, rs2	I
or	OR	rd, rs1, rs2	I
xor	eXclusive OR	rd, rs1, rs2	I
not	NOT	rd, rs	I
andn	ANDNot	rd, rs1, rs2	B
orn	ORNot	rd, rs1, rs2	B
xnor	Not XOR	rd, rs1, rs2	B
bclr	Bit CLeaR	rd, rs	B
bset	Bit SET	rd, rs	B
binv	Bit INVert	rd, rs	B
orc.b	OR Combine within Bytes	rd, rs	B
slli	Shift Left Logical Immediate	rd, rs, imm5/6	I
srli	Shift Right Logical Immediate	rd, rs, imm5/6	I
srai	Shift Left Arith Immediate	rd, rs, imm5/6	I
rori	ROtate Right Immediate	rd, rs, imm5/6	B
sll	Shift Left Logical	rd, rs1, rs2	I
srl	Shift Right Logical	rd, rs1, rs2	I
sra	Shift Right Arithmetic	rd, rs1, rs2	I
ror	ROtate Right	rd, rs1, rs2	B
rol	ROtate Left	rd, rs1, rs2	B
slliw	Shift Left Logical Word Immediate	rd, rs, imm5	I	x
slli.wu	Shift Left Logical Word (U in double) Immediate	rd, rs, imm5/6	I	x
sraiw	Shift Left Arith Word Immediate	rd, rs, imm5	I	x
srliw	Shift Right Logical Word Immediate	rd, rs, imm5	I	x
roriw	ROtate Right Word Immediate	rd, rs, imm5	B	x
sllw	Shift Left Logical Word	rd, rs1, rs2	I	x
srlw	Shift Right Logical Word	rd, rs1, rs2	I	x
sraw	Shift Right Arith Word	rd, rs1, rs2	I	x
rorw	ROtate Right Word	rd, rs1, rs2	B	x
rolw	ROtate Left Word	rd, rs1, rs2	B	x
clz	Count Leading Zeros	rd, rs	B
ctz	Count Trailing Zeros	rd, rs	B
cpop	Count POP	rd, rs	B
clzw	Count Leading Zeros in Word	rd, rs	B	x
ctzw	Count Trailing Zeros in Word	rd, rs	B	x
cpopw	Count POP in Word	rd, rs	B	x
j	Jump	label	I
jal	Jump And Link	rd, imm20	I
jr	Jump Register	rs [, imm12]	I
jalr	Jump And Link Register	rd rs [, imm12]	I
call	CALL	symbol	I
tail	TAIL call	symbol	I
ret	RETurn	-	I
beq	Branch ==	rs1, rs2, label	I
bne	Branch !=	rs1, rs2, label	I
blt	Branch <	rs1, rs2, label	I
bgt	Branch >	rs1, rs2, label	I
bge	Branch >=	rs1, rs2, label	I
ble	Branch <=	rs1, rs2, label	I
bltu	Branch < (U)	rs1, rs2, label	I
bgtu	Branch > (U)	rs1, rs2, label	I
bgeu	Branch >= (U)	rs1, rs2, label	I
bleu	Branch <= (U)	rs1, rs2, label	I
nop	NoOPeration	-	I
ecall	Environment CALL	-	I
ebreak	Environment BREAK	-	I

See also

• RISC-V assembly language
• x86 instruction listings