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Description Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. (In terms of the usual FPGA terminology then, Fs = 3.) The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.
Date
Source en:Image:Switch box.gif
Author Traced by User:Stannered from an work by en:User:Ignaciomella
Permission
(Reusing this file)		 GFDL
Other versions en:Image:Switch box.gif


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29 April 2007

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current16:31, 29 April 2007Thumbnail for version as of 16:31, 29 April 2007443 × 289 (13 KB)Stannered{{Information |Description=Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent

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