Draft:Chronologic Simulation
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Last edited by Bearcat (talk | contribs) 27 hours ago. (Update) |
 | This article relies largely or entirely on a single source. (May 2025) |
| Company type | Private |
|---|---|
| Headquarters | Los Altos, California, United States |
Key people |
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Chronologic Simulation, Inc. was a Los Altos, California, USA, based provider of Verilog HDL simulation products. Chronologic Simulation’s main product was VCS (Verilog Compiled Simulator). In 1994 Chronologic was sold to Viewlogic Systems and in 1997 Viewlogic was acquired by Synopsys, Inc. where VCS remains its main HDL simulation offering.
History
[edit]In the late 1980s and early 1990s integrated circuits were being designed and verified in Verilog HDL simulators. These simulators were focused on gate level speed and were implemented as language interpreters. Verilog HDL was proprietary and owned by Cadence Design Systems after their acquisition of Gateway Design Automation, the developers of Verilog.
There was competition to Verilog from the US DoD VHDL language that became an IEEE standard and in 1991 Cadence made the proprietary Verilog HDL public and created Open Verilog International (OVI) (later renamed Accellera) to standardize it.
The founders of Chronologic saw the opening up of Verilog as an opportunity to adopt software compiler techniques and create a fast compiled code Verilog simulator.
Founding and early Management team
[edit]- John Sanguinetti, CEO and founder
- Peter Eichenberger, CTO and founder
- Michael McNamara, VP Engineering
- Martin Harding, VP Sales
- Simon Davidmann, VP Europe
Product
[edit]The development of the Verilog Compiled Simulator (VCS) started in 1991 with early development by Sanguinetti, Eichenberger, and McNamara and by 1993 the first version was released and in use with commercial users and in education and research. VCS parses the Verilog source and using software compiler techniques creates compliable C code which is then subsequently compiled into executable to run the native host computer. The performance of existing Verilog simulators was excellent at the gate level but lacked needed speed at the RTL level. Chronologic's VCS focused in RTL speed and by using cycle based and complier optimization techniques was often reported as being 10-40times faster than other commercial products.