Circuit underutilization

Circuit underutilization refers to the incomplete utility of semiconductor grade silicon on a standarized mass produced circuit programmable chip, such as a gate array type ASIC, FPGA, or CPLD.

Gate array

In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.

FPGA

Due to the design components of FPGA into logic blocks, simple designs that underutilize a single block suffer from gate underutilization. Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them.<ref name="chipdes">, resulting in 40 times less density than of standard cellASICs.

CPLD

CPLD like FPGA, also suffer from similar issues.