Quad data rate
Quad data rate (or quad pumping) is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the rising and falling edges, and at two intermediate points between them. The intermediate points are defined by a 2nd clock that is 90° out of phase from the first. The effect is to deliver four bits of data per signal line per clock cycle.[1]
In a quad data rate system, the data lines operate at twice the frequency of the clock signal. This is in contrast to double data rate systems where the clock and data lines operate at the same frequency.[1]
QDR technology was introduced by Intel in their Willamette core Pentium 4 CPU, and is currently employed in their Atom, Pentium 4, Celeron, Pentium D, and Core 2 Processor ranges. This technology has allowed Intel to produce chipsets and microprocessors that can communicate with each other at data rates expected of the traditional FSB technology running from 400 MT/s to 1600 MT/s, while maintaining a lower and thus more stable actual clock frequency of 100 MHz to 400 MHz.[2]
See also
References
- ^ a b Lee Penrod (2007-08-21). "Double Pumping, Quad Pumping, and DDR". Understanding System Memory and CPU speeds: A layman's guide to the Front Side Bus (FSB). directron.com. Retrieved 2014-01-09.
- ^ Thomas Soderstrom (2006-07-26). "Quad Data Rate Northbridge Technologies (S478, S775)". tomshardware.com. Retrieved 2014-01-09.
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