Talk:Cache hierarchy

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Copy edit needed

Much of the grammar on this page is very poor. It shows good technical knowledge, but was clearly written by a non-native speaker. TV4Fun (talk) 03:24, 7 November 2017 (UTC)[reply]

Second the comment above, on top of that the article needs some serious fact checking as well, there are number of things that I could dispute (mostly context-less generalizations).

"The access time to memory that acts as a bottleneck for the CPU core performance can be relaxed by using a hierarchical cache structure in order to reduce the latency and hence speed up the CPU clock.[1]"

Not only this has some serious "engrish" problems, I could argue that both sides of the implication are inaccurate (and while [1] ain't any peer reviewed and approved source, technically it doesn't say it either). Never mind that most people won't understand the meaning of terms like "relaxing"/"bottleneck" even means in the context. Semantics aside, the whole sentence is just plain BS, especially the part about speeding up the CPU clock (obvious BS) + it doesn't account for concepts like pipelining and fact that there are multiple stages of what is generalized here as "memory access".

There are whole lot more of these in the text, perhaps somebody with wiki account should suggest this for deleting or something. --86.49.254.166 (talk) 23:36, 20 January 2018 (UTC)[reply]

I concur completely, noticed this on first read of the article Rejewskifan (talk) 23:31, 27 May 2018 (UTC)[reply]

Confusion between higher and lower level

"Modern processors have split caches, and in systems with multilevel caches higher level caches may be unified while lower levels split." - in this line I believe higher and lower should be switched to match the diagram? 131.111.5.132 (talk) 15:52, 15 May 2024 (UTC)[reply]