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Show new changes starting from 15:02, 4 May 2025

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3 May 2025

diffhist PCI Express 09:31 −3 57.138.148.198 talk (→PCI Express OCuLink) Tag: Visual edit
diffhist PCI Express 09:26 −6 57.138.148.198 talk (→Slot power) Tag: Visual edit
diffhist PCI Express 09:20 +2 57.138.148.198 talk (→6- and 8-pin power connectors) Tag: Visual edit
diffhist PCI Express 09:15 +6 57.138.148.198 talk (→Non-standard video card form factors) Tag: Visual edit
diffhist PCI Express 09:10 −6 57.138.148.198 talk (→Interconnect) Tag: Visual edit
diffhist PCI Express 08:00 +1 Zac67 talk contribs (a lane is a dual simplex pair, see Base Spec, Terms and Acronyms)
diffhist m Serial port 04:54 +3 Dondervogel 2 talk contribs (→Speed: correct error in unit symbol)
diffhist PCI Express 00:25 −4 57.138.148.198 talk (→6- and 8-pin power connectors) Tag: Visual edit

2 May 2025

diffhist PCI Express 23:20 +6 57.138.148.198 talk (→48VHPWR connector) Tag: Visual edit
diffhist PCI Express 15:16 −11 57.138.148.198 talk Tag: Visual edit
diffhist Industry Standard Architecture 09:44 +977 Adrianwo talk contribs (→Past and current use)

29 April 2025

diffhist USB 20:29 +222 Stephan Leeds talk contribs (→Release versions: clarification and explanation of two-lane operation and requirements)
diffhist m USB 15:17 −2 Paul2520 talk contribs (clears CS1 date error(s) (via WP:JWB))
diffhist m USB 04:43 0 Glenn talk contribs (→References: small ref translation)
diffhist m USB 04:42 +2 Glenn talk contribs (→Connector type quick reference: wiki)
diffhist m USB 04:41 +1,264 Glenn talk contribs (+ref small addition)

28 April 2025

diffhist USB 15:05 +7 IngenieroLoco talk contribs (→Connector type quick reference)
diffhist m IEEE 1284 13:28 +495 Cutlass talk contribs (Reverted edits by 195.65.152.138 (talk) (AV)) Tags: AntiVandal Rollback
diffhist IEEE 1284 13:27 −495 195.65.152.138 talk Tag: Reverted

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