Related changes

30 June 2025

• diffhist Pentium 18:52 −36 5.43.104.164 talk (Intel Pentium was discountined in 2023) Tags: Manual revert Mobile edit Mobile web edit
• diffhist Itanium 15:52 −4 216.164.92.61 talk (→Inception: 1989–1994)

29 June 2025

• diffhist Intel 8080 16:16 −4 RastaKins talk contribs (Moved "Patent on 8080" section. Always seemed odd that it was tacked onto the very end of the article. Perhaps it should not be its own section?)
• diffhist m TSMC 15:21 +225 EchoEc talk contribs (add another citation) Tag: Visual edit
• diffhist m TSMC 15:19 +167 EchoEc talk contribs (Add reference: taiwannews) Tag: Visual edit
• diffhist m TSMC 15:14 +4 EchoEc talk contribs (add internal link to Tokyo Laboratory) Tag: Visual edit
• diffhist m TSMC 15:11 +280 EchoEc talk contribs (Add 2025 TSMC collaboration with UTokyo Lab) Tag: Visual edit
• diffhist Central processing unit 15:08 +255 14.151.17.224 talk (→Microprocessors)
• diffhist Intel Core 14:34 +140 14.151.17.224 talk (→Core and Core Ultra 3/5/7/9)
• diffhist Neural processing unit 14:24 +181 240e:47d:1af9:d214:ed15:eb2a:1a4c:dcd9 talk (→Use: Intel Core Ultra and AMD Ryzen AI are included NPU.)
• diffhist m Pentium (original) 01:57 0 BrainyWoolf talk contribs (Corrected "P45C" to "P54C".) Tags: Visual edit Mobile edit Mobile web edit

28 June 2025

• diffhist Reduced instruction set computer 23:01 +1,425 PaulBoddie talk contribs (→Commercial breakout: Adjusted the details of early implementations, noting that the ARM1 was fabricated in 1985 but wasn't introduced until 1986. If first samples of chips were considered "firsts", we would have to start backdating everything. Added PA-RISC reference.)
• diffhist Complex instruction set computer 22:17 +291 Ylee talk contribs (→CISC and RISC terms: Intel did improve x86)
• diffhist Reduced instruction set computer 20:55 +17 Guy Harris talk contribs (→Commercial breakout: Sun would have to have licensed the 68k ISA and build their own 68k processors to improve CISC on their own; otherwise, they'd have to rely on Motorola. (Switching to their own instruction set also let them design processors on their own.))
• diffhist Reduced instruction set computer 20:46 +72 Ylee talk contribs (→Commercial breakout: Clarify/reword)
• diffhist Complex instruction set computer 20:19 +12 Guy Harris talk contribs (→CISC and RISC terms: For x86 and 68k, go with the series, not just particular processors. (PDP-10 and PDP-8 refer to series, as do IBM Z (updated from System z) and VAX.)
• diffhist Complex instruction set computer 20:16 +11 Guy Harris talk contribs (→CISC and RISC terms: Sun only briefly used the 68000; they switched to the 68010 as soon as possible, so that they could support 4.2BSD demand paging without Apollo-style dual-processor tricks, and then switched to the 68020 and finally 68030.)
• diffhist Complex instruction set computer 20:12 −37 Guy Harris talk contribs (→CISC and RISC terms: {{citation needed}} and {{failed verification}} do not go together - {{failed verification}} means that the source doesn't support the claim, so at least there's a source; {{citation needed}} means there isn't a source.)
• diffhist Complex instruction set computer 20:10 −11 Guy Harris talk contribs (→CISC and RISC terms: Also chosen by NexGen and AMD for x86, so just say "and x86".)
• diffhist Reduced instruction set computer 19:33 +1,002 Ylee talk contribs (→Commercial breakout: CISC vendors' response to RISC)
• diffhist Complex instruction set computer 19:23 +884 Ylee talk contribs (→CISC and RISC terms: CISC's response to RISC)
• diffhist m 5 nm process 06:16 +3 GünniX talk contribs (v2.05 - Fix errors for CW project (Unbalanced quotes in ref name or illegal character or empty name.)) Tag: WPCleaner
• diffhist Panther Lake (microprocessor) 04:00 −307 Peetel talk contribs (Copilot (LLM) used as source) Tag: 2017 wikitext editor

27 June 2025

• diffhist Intel 8080 22:18 +1 RastaKins talk contribs (→Pin use: Conform WR- pin to chip illustration)
• diffhist Reduced instruction set computer 21:36 +28 Guy Harris talk contribs (→Commercial breakout: It's Power ISA now.)
• diffhist Reduced instruction set computer 20:20 +597 Ylee talk contribs (→Commercial breakout: DECstation example)
• diffhist m Instruction set architecture 19:12 −31 LightlySeared talk contribs (Reverted 1 edit by 78.149.38.121 (talk) to last revision by RastaKins) Tags: Twinkle Undo
• diffhist Instruction set architecture 19:12 +31 78.149.38.121 talk Tag: Reverted
• diffhist 64-bit computing 08:07 +282 125.90.10.178 talk (→History)
• diffhist 5 nm process 06:28 +245 Alawadhi3000 talk contribs (→4 nm process nodes: Intel 4 update)
• diffhist 7 nm process 06:23 −259 Alawadhi3000 talk contribs (→Process nodes and process offerings: Intel 7 update)

26 June 2025

• diffhist StrongARM 22:38 −3 Microxstephn talk contribs (→SA-1110: edited for clarity) Tags: Mobile edit Mobile web edit
• diffhist StrongARM 22:37 +4 Microxstephn talk contribs Tags: Mobile edit Mobile web edit
• diffhist StrongARM 22:36 −19 Microxstephn talk contribs (→SA-1100: syntax improvement) Tags: Mobile edit Mobile web edit
• diffhist Tick–tock model 09:54 −9 57.138.148.198 talk (→Atom roadmap) Tag: Visual edit
• diffhist Intel 8085 02:34 +30 RastaKins talk contribs (Lead: The four new interrupt pins were more important than the "serial port" which really isn't a serial port. They used up more pins, too.)
• diffhist Intel 8080 00:28 +697 RastaKins talk contribs (Added section on interrupts)
• diffhist Intel 8080 00:08 +77 RastaKins talk contribs (→Pin use: Added Intel's names for the processor state lines)

25 June 2025

• diffhist Pentium Pro 22:06 −2 Guy Harris talk contribs (→Summary: Get rid of redundant :80. Have url= match what's in archive-url=.)
• diffhist Intel 8086 01:03 −8 RastaKins talk contribs (→The first x86 design: While the 8086 shares a similar architecture, 8086 does not have a MICROarchitecture similar to 08/80/85. 8086 has prefetching bus interface unit, execution unit, none of which those processors had.)
• diffhist m CPU cache 00:25 0 GreenDevolution talk contribs (Minor fix to make use of higher/lower level consistent) Tag: Visual edit

24 June 2025

• diffhist CPU cache 14:57 +66 GreenDevolution talk contribs (Make usage of higher/lower cache levels consistent. Hennessy and Patterson describe L1 cache as the highest-level cache.) Tag: Visual edit
• diffhist m Intel 8008 13:54 +1 RastaKins talk contribs (→Interrupts: plural)
• diffhist P6 (microarchitecture) 12:50 0 Finlay McWalter talk contribs (→Features: ordinary caps)
• diffhist m X86-64 12:06 −8 Regestriruisa talk contribs
• diffhist TSMC 09:15 0 183.78.90.182 talk Tags: Mobile edit Mobile web edit
• diffhist Binary-coded decimal 08:51 −16 141.47.39.115 talk (→Disadvantages: "per cent" replaced with simple %) Tag: Visual edit
• diffhist Intel 8088 04:05 +286 RastaKins talk contribs (→Peripherals: Added some peripheral chips found in the original IBM PC.)
• diffhist Intel 8086 02:43 +2 RastaKins talk contribs (→Interrupts: Downgraded interrupts so they appear under details)
• diffhist Intel 8086 02:25 +1,680 RastaKins talk contribs (Added new section on interrupts)