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26 July 2025
- diffhist Single instruction, multiple data 11:10 +50 Lkcl talk contribs (→Chronology: highlight that ILLIAC IV was made up of scalar 64-bit PEs not SIMD PEs) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 11:06 +52 Lkcl talk contribs (Array Processors do not ''have'' to have Processing Elements that are SIMD themselves.) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 11:03 +55 Lkcl talk contribs (mention SIMD lanes and clarify a little by mentioning SWAR) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Real number 00:05 +26 Ammrat13 talk contribs (→Sources: Use `refbegin` and `refend`)
25 July 2025
- diffhist Single instruction, multiple data 13:16 +73 Lkcl talk contribs (add see also for SWAR and SIMT) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 13:09 +82 Lkcl talk contribs (→History: Early true-vector processors were not SIMD. they did vector chaining. VPs were too complex and inspired SWAR.) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 12:51 +192 Lkcl talk contribs (mention control signals) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 12:42 +233 Lkcl talk contribs (added screenshot from ARPA-funded "unlimited distribution" document, July 15 1971, just for fits and giggles. the image is also used in an academic paper) Tags: Mobile edit Mobile web edit Advanced mobile edit
- diffhist Single instruction, multiple data 12:38 −242 Lkcl talk contribs (add ILLIAC IV reference. nyer nyer to NVIDIA who claimed they were first. sorry, ILLIAC beat ya by 50 years :)) Tags: Mobile edit Mobile web edit Advanced mobile edit