Through-silicon via (TSV)
In electronical engineering, a through-silicon via (TSV) is a vertical electrical connection passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits.
TSV technology in 3D packages
A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edges; this edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking).
TSV technology in 3D ICs
A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small “footprint.” In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation.
Capacitive coupling to substrate
Since the TSV is a metal contact separated from the silicon substrate by a dielectric, it acts as a capacitor connection to the substrate. Hence for high-speed operation (e.g., GHz or faster frequencies), this capacitive coupling impedance is reduced dramatically, allowing crosstalk to adjacent TSVs.