SystemVerilog
| 编程范型 | Structured (design) Object-oriented (verification) |
|---|---|
| 发行时间 | 2002年 |
| 型態系統 | Static, weak |
| 文件扩展名 | .sv |
| 受影响于 | |
| Verilog, Vera | |
在集成电路设计中, SystemVerilog是一个集成了硬件描述语言和硬件验证功能的综合工具，它是以Verilog为基础的。
参考文献
- Project VeriPage. Project VeriPage. 1997-06-06.
- McGrath, Dylan. IEEE approves SystemVerilog, revision of Verilog. EE Times. 2005-11-09 [2007-01-31].
- Puneet Kumar. System Verilog Tutorial. 2005-11-09.
- Gopi Krishna. SystemVerilog ,SVA,SV DPI Tutorials. 2005-11-09.
- HDVL. More SystemVerilog Weblinks.
- Spear, Chris, "SystemVerilog for Verification" Springer, New York City, NY. ISBN 0-387-76529-8
- Sutherland, Stuart, Davidmann, Simon, Flake, Peter "SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling" Springer, New York City, NY. ISBN 0-387-33399-1
- SystemVerilog Assertions Handbook, 2nd Edition - http://SystemVerilog.us
- A Pragmatic Approach to VMM Adoption - http://SystemVerilog.us
外部链接
IEEE S标准文献
- 1800-2009 IEEE Standard for System Verilog-Unified Hardware Design, Specification, and Verification Language
- SystemVerilog 3.1a Language Reference Manual - 2004 draft version, which is before IEEE 1800-2005 standard.
教程
标准开发
- IEEE P1800 – Working group for SystemVerilog
- Sites used before IEEE 1800-2005
语言延伸
- Verilog AUTOs - An open-source meta-comment system to simplify maintaining Verilog code.