User:Jfishburn/Intentional Clock Skew in Synchronous Circuits
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Intentional clock skew is clock skew that is deliberately designed into a Synchronous circuit to armor it against various kinds of failure, or to enable it to be clocked at a higher rate.
Ideal Clocking with Zero Clock Skew
What Can Go Wrong
SETUP Failure
HOLD Failure
The Nightmare Scenario: Intermittent HOLD Failure
For Low-Delay Paths, The Perils of Zero Clock Skew
A Logic Path with Little Or No Delay Is Close to HOLD Failure
A Small Amount of Unintentional Skew Causes It To Fail
Intentional Clock Skew To the Rescue
Intentional Clock Skew Can Also Speed Up A Circuit
References
External links