Talk:CPU cache
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 | The contents of the Tag RAM page were merged into CPU cache on 4 November 2016. For the contribution history and old versions of the redirected page, please see its history; for the discussion at that location, see its talk page. |
| The contents of the Smart Cache page were merged into CPU cache on 28 March 2019. For the contribution history and old versions of the redirected page, please see its history; for the discussion at that location, see its talk page. |
Merger
There was an apparent merger with the L1, L2, and L3 caches of a CPU. I would like it if there were sections depicting each or at least a section that explains them. — Preceding unsigned comment added by Laboye (talk • contribs) 14:49, 20 September 2006 (UTC)
Image:Cache,associative-read.png
I find it confusing that the same word (index) denotes both tags in the Tag SRAM and words in the Data SRAM. Index often denotes the part of address used for selecting the whole cache line (Addr[10:6]), which is not the same as the part used for addressing the Data SRAM (Addr[10:2]) as shown in the image.
Usually people draw the index field connected to a decoder which selects the line. The relevant portion of the line is finally extracted by an additional decoder, which is addressed by the offset field of the address.
The detached organization in the image is also fine, but the words "index" in each line seem redundand and confusing.
Perhaps you could attribute Data SRAM entries as word 0, word 1, etc, and the Tag SRAM entries as tag 0, tag 1, etc? — Preceding unsigned comment added by 161.53.65.130 (talk • contribs) 10:47, 17 November 2008 (UTC
Other caches??
- L0 - on slides of AMD's RDNA3 architecture
- K cache - on slides of AMD's RDNA3 architecture
- RB cache- on slides of AMD's RDNA3 architecture
- Write cache [1]
37.205.108.123 (talk) 14:09, 24 March 2024 (UTC)
- 3D cache / stacked cache [2]
- V-Cache [3] — Preceding unsigned comment added by Setenzatsu.2 (talk • contribs) 17:50, 25 March 2024 (UTC)
- Are "3D caches"/"stacked caches"/"vertical caches"/etc. just different packaging/interconnects for CPU caches? Guy Harris (talk) 18:15, 25 March 2024 (UTC)
Predecoding
Predecoding is mentioned in passing, but there is no metion of what it is or a link to something that explains it. Mark (talk) 23:01, 6 May 2025 (UTC)
- As far as I know, it's referring to storing in an instruction cache more than just cache lines containing raw instruction data loaded from memory, so that the instruction decoder has less work to do if the instruction is fetched from the cache, but that probably would need - and should have - a section of its own to explain it. Guy Harris (talk) 05:23, 7 May 2025 (UTC)