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Multigate device

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A multigate device refers to a MOSFET which incorporates more than one gate into a single device. Multigate transistors are one of several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells, colloquially referred to as extending Moore's Law.[1] Development efforts into multigate transistors have been reported by AMD, IBM, Infineon, Intel, TSMC, and others. Other complementary strategies for device scaling include channel strain engineering, silicon-on-insulator-based technologies, and high-k/metal gate materials.

Varieties

Dozens of multigate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and number of gates (2, 3, or 4).

Planar Double Gate Transistors

Planar double-gate transistors employ conventional planar (layer by layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures.

FinFETs

The term FinFET was coined by Hitachi engineer Digh Hisamoto to describe a nonplanar, double-gate transistor built on an SOI susbtrate,[2], based on the earlier DELTA (single-gate) transistor design. [3] The distinguishing characteristic of the FinFET is that the conducting channel is wrapped around a thin silicon "fin", which forms the body of the device. The dimensions of the fin determine the effective channel length of the device.

In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD and IBM describe their double-gate development efforts as FinFET development whereas Intel avoids using the term to describe their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates.

References

  1. ^ Risch, L. "Pushing CMOS Beyond the Roadmap", Proceedings of ESSCIRC, 2005, p. 63
  2. ^ Hisamoto, D. et al (2000) "FinFET - A Self-Aligned Double-Gate MOSFET Scalable to 20 nm" IEEE Trans. Electron. Dev. 47 (12) p. 2320.
  3. ^ Hisamoto, D. et al (2000) "Impact of the vertical SOI 'Delta' Structure on Planar Device Technology" IEEE Trans. Electron. Dev. 41 p. 745.