Talk:Reduced instruction set computer

Article improvements

In view of the above, I wrote a couple of quick missing articles on load/store vs register/memory architectures etc. that needed to be linked from here. I also fixed the lede. I think the best way to fix the article now is to use a "reduced diversion approach" and just state the basic elements in fully sourced form.

I will start by reducing the history discussions to the basics, add sources etc. and move it upfront. Then discuss the motivation, compilation issues, etc. and eventually work up to the mobile issues etc.

But mobile RISC is not the whole story and the article should also point out that RISC is not just for cell phones and the 8 petaflops K computer (fastest on the TOP500 as of this writing) also uses the SPARC64 - a RISC architecture. So RISC now dominates the low ground in cell phones and some of the high ground on the TOP500. That will shed light on the flexibility of the architecture.

Anyway, I will begin the fixes and move sections according to that plan. If there are suggestions, just post below here and we can discuss it. Thanks. History2007 (talk) 12:58, 21 March 2012 (UTC)

It would be nice if the history of RISC also mentioned that other RISC product from the other side of the pond: ARM. John Allsup (talk) 00:26, 24 April 2013 (UTC)

Just Do It. Guy Harris (talk) 01:01, 24 April 2013 (UTC)

ROMP a single-chip 801?

The article says "The 801 was eventually produced in a single-chip form as the ROMP in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'." The documents "The 801 Minicomputer - An Overview" and "System 801 Principles of Operation" describe a machine with 24-bit registers, but the "RT PC Technical Reference, Volume 1" describes a machine with 32-bit registers. Was there a later machine in the 801 family that looked like the ROMP? Guy Harris (talk) 01:03, 22 March 2012 (UTC)

I really do not remember the details of the 801 family follow ups now - it was long ago... Is there an error in what the article says? I do not see one. The Jurij Šilc reference I looked up for the 801 only refers to the 32 bit. They may have played with a few systems, I am not sure now. But just fix it if you see an error. Thanks. History2007 (talk) 01:27, 22 March 2012 (UTC)

By the way, the Wikipedia ROMP article (which happens to be reference free) says: "The original ROMP had a 24-bit Reduced Instruction Set Computer (RISC) architecture developed by IBM, but the instruction set was changed to 32 bits a few years into the development." So that may be the case, but that is probably too much detail for this article given that the 801 did not go that far on its own. History2007 (talk) 02:04, 22 March 2012 (UTC)

I was asking a question, not making an assertion; not having been in IBM Research or in the group(s) that did ROMP, I don't know what the full history of the 801 or ROMP was. I've asked in the ROMP article for some citations; more history on the 801 and ROMP would be interesting (but might require help from somebody who was inside IBM at the time). Guy Harris (talk) 07:05, 22 March 2012 (UTC)

Ok, no problem. But the ROMP article itself needs serious help and I will hence not even look at it again so I will not even be tempted to fix it. I did not even want to fix this one until some user shifted the tags etc. So I will do my best not to think of ROMP, at a time when Processor register needs so much more help.... I posted for help on WikiProj computing about this page and Processor register, but I am not holding my breath that it will get fixed soon that way... History2007 (talk) 08:18, 22 March 2012 (UTC)

iPad, but not smartphones?

The article says "In the 21st century, the use of ARM architecture processors in the Apple iPad provided a wide user base for RISC-based systems." Is the idea here that the iPad (and, potentially, other ARM-based tablets, depending on the success of, for example, Android or Windows 8) are more like "real computers" than smartphones are, so people are more likely to think of them as "computers"? Guy Harris (talk) 01:05, 22 March 2012 (UTC)

Reasonable comment actually. Shows that I don't think of cell phones as real computers. Please fix that to represent the views of the modern generation for whom cell phones are computers. But the general idea is that RISC now runs $800 computers to $80 million systems. That is the message. History2007 (talk) 01:30, 22 March 2012 (UTC)

I have now done a first set of fixes to the lede and the first section, added refs, etc. and will take a break. So please check that, fix items, etc. Thanks. History2007 (talk) 01:48, 22 March 2012 (UTC)

Anyway, I fixed it now so it says smartphone as well. History2007 (talk) 08:39, 22 March 2012 (UTC)

Design Philosophy and Berkeley RISC Article

Reading through the article, I didn't find it adequately answered questions like "Why was RISC designed?", "What problem(s) did it solve, and what was conceived to solve the problem(s)?"

I expected these questions would be answered in the "Instruction Set Philosophy" section, but it headlines by stating that RISC isn't a dumb idea, even though the acronym includes the word "reduced". The "Instruction Set Philosophy" section fails at describing the RISC "Instruction Set Philosophy" to people lacking prior knowledge of RISC. The best information I found about RISC on Wikipedia was in the "RISC Concept" section of the Berkeley RISC article. But that section of the article links back to this one as the main article. This is a problem because it contains plenty of information that this article does not, however, without references (at least not with any inline citations). On the talk page of the Berkeley RISC article, there is discussion about removing the "RISC Concept" section of that article because it "is most probably redudant" with this article, but again, this is not true. If references for that information can be found, that information should be moved to this article and a less in-depth summary written for the Berkeley RISC article. I don't yet possess an adequately comfortable working knowledge of RISC or Berkeley RISC to volunteer for this duty, but I hope someone can find my observations useful. Wurtech (talk) 18:18, 27 February 2017 (UTC)

Locked In ?

The article says users of "PC" were locked into intel x86. However C compilers compiled code that had run on risc machines. x86 has emulators. CPUs with the feature of uploading new microcode came on the market long ago. i think "locked in" is a bit strong - never really true. — Preceding unsigned comment added by 72.209.223.190 (talk) 03:56, 14 July 2015 (UTC)

A C compiler doesn't help if:

• your code isn't written in C (applications for DOS/Windows were also written in assembler, Turbo Pascal, etc., and DOS and (non-NT) Windows themselves had a significant amount of assembler code);
• your code assumes it's running on a little-endian processor, or a processor that doesn't require strict alignment of data;

etc., so a C compiler for your instruction set is not a magic bullet. Yes, there were x86 emulators, but that didn't manage to make, for example, Alpha able to compete with x86.

And "the ability to upload new microcode" isn't the same thing as "the ability to run arbitrary instruction sets well", if that's what you're trying to say with "CPUs with the feature of uploading new microcode came on the market long ago." Most RISC CPUs didn't even have microcode, so it's not as if they could be microcoded into running x86 well, and even most microcoded CISC CPUs have instruction fetch paths that are rather oriented towards executing a particular instruction set. Guy Harris (talk) 07:01, 14 July 2015 (UTC)

History - What about ARM?

The article describes the history of the MIPS and SPARC processors in the early 1980s, but what about ARM, which was being developed around the same time?

The ARM (at the time an abbreviation of Acorn RISC Machine) project began in 1983 and the first silicon was delivered in 1985. In 1987 a PC containing an ARM processor was sold under the name "Acorn Archimedes".

It seems to me to be worth mentioning ARM's part in the history of RISC, coming at it from a different angle - much lower-end chips than SPARC and MIPS, which were destined for workstations. Since ARM's designs have since become ubiquitous, I think they are worthy of a greater mention than they get in this article. Marchino61 (talk) 00:10, 4 July 2016 (UTC)

Requested move 10 May 2017

The following is a closed discussion of a requested move. Please do not modify it. Subsequent comments should be made in a new section on the talk page. Editors desiring to contest the closing decision should consider a move review. No further edits should be made to this section.

The result of the move request was: Moved.Granted as a non-controversial request.(non-admin closure) Winged Blades ^Godric 05:56, 19 May 2017 (UTC)

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Reduced instruction set computing → Reduced instruction set computer – This article was moved here from its previous title at Reduced instruction set computer on 20 April 2010 without any prior discussion to seek consensus. The only rationale was given in the edit summary: "intruductory [sic] paragraph's wording is awkward and more easily addresses RISC as an architecture ("… computing") than an instance of it's use ("… computer")."

I contend that this is incorrect. Whatever compositional problems the lead had, the solution cannot be to represent this topic as being called "reduced instruction set computing" when it is not. To do so would be to misrepresent the topic and what the topic is commonly called, thus introducing factual inaccuracies. The term "RISC" was introduced in David Patterson and David R. Ditzel's "The case for the reduced instruction set computer" (ACM SIGARCH Computer Architecture News, V. 8, No. 6, October 1980). Since then, that is what RISCs have been called. The idea that using "computing" instead of "computing" creates a distinction between "architecture" and an instance of its use is incorrect. The use of "computer" instead of "computing" in RISC is no different to that in terms such as "stored-program computer". One does not see instances of "stored-program computing". 50504F (talk) 07:23, 10 May 2017 (UTC)

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The above discussion is preserved as an archive of a requested move. Please do not modify it. Subsequent comments should be made in a new section on this talk page or in a move review. No further edits should be made to this section.

Problems with the lead

The lead presently says:

Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction. A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing (CISC).

There's a few problems here besides the issue raised at Talk:Reduced instruction set computer#Requested move 10 May 2017:

• To say that RISC is a CPU design strategy could be misunderstood by laypeople as self-contradictory given that a CPU is understood to be a part of a computer, yet the "C" in "RISC" means "computer". A person familiar with the topic would understand that whilst some sources describe RISC as such, its because of the inadequacies of the language in reconciling how the idea was originally framed and how it is framed today. RISC is better described as a type of computer.
• "Microprocessor architecture" implies that RISC is intrinsically linked to microprocessors. Whilst that's the popular narrative, it's wrong. The first RISC was the IBM 801, and it wasn't a microprocessor.
• "Microprocessor architecture" is linked to "microarchitecture"; "microarchitecture" is not a contraction of "microprocessor architecture".
• The use of cycles per instruction (CPI) to mean instruction latency is completely wrong. To speak very generally, CPI is an average of all measured instruction latencies.
• "Microprocessor cycles per instruction" is meaningless, there's no need to qualify "CPI" with "microprocessor".

I've improved the lead as best I can, but given the complexity of the topic, it's probably still be inadequate. 50504F (talk) 07:35, 26 May 2017 (UTC)

What about PowerMacs using PowerPC processors from IBM for many years, G3, G4, G5...

It seems the article is not mentioning probably the biggest user of RISC processors, APPLE. In the 90s all Macs were powered by IBM RISC PowerPC processors, then the transition to Intel happened in the early 2000s... — Preceding unsigned comment added by 193.105.48.90 (talk) 13:37, 6 June 2017 (UTC)

Article implies performance parity with x86 throughout without providing data to back up that claim

This article repeatedly makes the reader believe there is performance parity between RISC and CISC computers, forcing itself to take a very ignorant look at computing as a whole in order to accomplish that goal. For example...

"The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[24]"

Despite the complexity of CISC instructions, modern CISC computers can execute between 3-4 IPC (instructions per cycle). Source: https://lemire.me/blog/2019/12/05/instructions-per-cycle-amd-versus-intel/

If we look at the manual for a common RISC CPU like the SiFive E21, we can see that..... “The pipeline has a peak execution rate of one instruction per clock cycle.” Source: https://sifive.cdn.prismic.io/sifive%2Fc93c6f29-5129-4e19-820f-8621300eca53_e21-core-complex-manual-v19.05.pdf

So despite having less complex instructions, RISC processors in practice still can't execute more instructions than their CISC counterparts. Additionally, CISC computers don't have to "translate" or "emulate" 90% of the code in existence. So they have the home-field advantage over RISC which must waste clock cycles to emulate the x86 instruction set. The emulation of x86 software is not a value-added feature of CISC to the user. It is a non-value-added feature that only exists to enable the CPU to do work most existing CISC computers can do natively.

Please modify the article to at least acknowledge the substantial performance difference between CISC and RISC. Also, please refrain from seeking to marginalize the substantial technological benefits of using CISC technology. I understand this is a RISC article, but it's disingenuous to represent RISC as an apples-to-apples comparison to CISC. It clearly isn't. You have the entire "energy efficiency" soap-box to stand on but you choose not to use it. Instead you stand on the performance soap-box trying to sell CISC-like capabilities under the RISC flag while somehow ignoring the fact that CISC still exists, and is still actually still more performant than RISC. Source: https://images.idgesg.net/images/article/2020/12/m1_cinenbench_r20_nt-100870777-orig.jpg