Program status word

The program status word (PSW) is a register in the IBM System/360 architecture and successors that performs the function of a status register and program counter in other architectures, and more. The term is also applied to a copy of the PSW in storage.

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 2³ + 2² + 2¹ + 2⁰. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

• Interrupt masks
• Privilege states
• Condition code
• Instruction address

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

Format

S/360

S/360 PSW

00 07 08 15 16 23 24 31 32 39 40 47 48 57 58 63 (bit position)* Standard S/360 Program Status Word SM Key AMWP IC ILC,CC PM IA S/360 PSW PSW abbreviations Field Meaning SM System Mask Bit Meaning 0 Channel 0 mask 1 Channel 1 mask 2 Channel 2 mask 3 Channel 3 mask 4 Channel 4 mask 5 Channel 5 mask 6 I/O mask, channels 6-15 7 External Interrupt mask A ASCII mode M Machine-Check Mask W Wait State P Problem State IC Interrupt Code ILC Instruction Length Code CC Condition Code PM Program Mask Bit Meaning 36 Fixed-point overflow 37 Decimal overflow 38 Exponent underflow 39 Significance IA Instruction Address Extended PSW mode Program Status Word (360/67 only) SM Key AMWP ILC,CC PM spare IA Extended PSW mode PSW Extended PSW mode PSW abbreviations Field Meaning SM Modes and System Mask Bit Meaning 0-3 0000 4 24/32-Bit Address Mode 5 Translation Control 6 I/O Mask (Summary) 7 External Mask (Summary) A ASCII mode M Machine-Check Mask W Wait State P Problem State ILC Instruction Length Code CC Condition Code PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance IA Instruction Address Note: IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

S/370

S/370 PSW

00 07 08 15 16 23 24 31 32 39 40 47 48 57 58 63 (bit position)* Basic Control mode Program Status Word SM Key EMWP IC ILC,CC PM IA BC mode PSW BC mode PSW abbreviations Field Meaning SM System Mask Bit Meaning 0 Channel 0 mask 1 Channel 1 mask 2 Channel 2 mask 3 Channel 3 mask 4 Channel 4 mask 5 Channel 5 mask 6 I/O mask, channels 6-15 7 External Interrupt mask E=0 BC mode M Machine-Check Mask W Wait State P Problem State IC Interrupt Code ILC Instruction Length Code CC Condition Code PM Program Mask Bit Meaning 36 Fixed-point overflow 37 Decimal overflow 38 Exponent underflow 39 Significance IA Instruction Address Extended Control mode Program Status Word (S/370 mode) 0R00 0TIOEX Key EMWP S0,CC PM 00000000 00000000 IA EC mode PSW (S/370) EC mode PSW (S/370) abbreviations Field Meaning R PER Mask T DAT Mode IO I/O Mask; subject to channel mask in CR2 EX External Mask; subject to external subclass mask in CR0 E=1 EC mode M Machine-Check Mask W Wait State P Problem State S Address-Space Control 0=primary-space mode, 1=secondary-space mode CC Condition Code PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance IA Instruction Address Note: IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

S/370 Extended Architecture (S/370-XA)

S/370 Extended Architecture

00 07 08 15 16 23 24 31 32 39 40 47 48 57 58 63 (bit position)* Extended Control mode Program Status Word (S/370-XA mode) 0R00 0TIOEX Key EMWP S,0,CC PM 00000000 A, IA EC mode PSW (S/370-XA) EC mode PSW (S/370-XA) abbreviations Field Meaning R PER Mask T DAT Mode IO I/O Mask; subject to channel mask in CR2 EX External Mask; subject to external subclass mask in CR0 E=1 EC mode M Machine-Check Mask W Wait State P Problem State S Address-Space Control 0=primary-space mode, 1=secondary-space mode CC Condition Code PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance A size of effective Address (bit 32) 0=24, 1=31 IA Instruction Address (bits 33-63) Note: IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

Enterprise Systems Architecture (ESA)

Enterprise Systems Architecture PSW formats

00 07 08 15 16 23 24 31 32 39 40 47 48 57 58 63 (bit position)* Extended Control mode Program Status Word (S/370-ESA mode) 0R00 0TIOEX Key EMWP AS,CC PM 00000000 00000000 S, IA EC mode PSW (S/370-ESA) EC mode PSW (S/370-ESA) abbreviations Field Meaning R PER Mask T DAT Mode IO I/O Mask; subject to channel mask in CR2 EX External Mask; subject to external subclass mask in CR0 E=1 EC mode M Machine-Check Mask W Wait State P Problem State AS Address-Space Control (bits 16-17) 00=primary-space mode 01=Access-register mode 10=Secondary-space mode 11=Home-space mode CC Condition Code (bits 18-19) PM Program Mask Bit Meaning 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance A size of effective Address (bit 32) 0=24, 1=31 IA Instruction Address (bits 33-63) Note: IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

References

S360

IBM System/360 Principles of Operation (PDF) (Eighth ed.). IBM. September 1968. A22-6821-7.

func67

IBM System/360 Model 67 Functional Characteristics (PDF) (Third ed.). IBM. February 1972. GA27-2719-2.

S370

IBM System/370 Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. A22-7000-10.

S370-XA

IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1.

S370-ESA

IBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0.

z

z/Architecture Principles of Operation (PDF) (Tenth ed.). IBM. September 2012. SA22-7832-09.