Jump to content

Load–store architecture

From Wikipedia, the free encyclopedia
This is an old revision of this page, as edited by 103.142.69.134 (talk) at 17:29, 16 December 2020 (my oll in oll wapsid wikipeday page add my foll addresh and my paymbt naxt use and case and caseh back met infom my hand payment jast i do nit it mene ok). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

In [[computer 

(https:and url 40*Yes im sobujmia  my ragestar confom link add wikpeday ssobujmia@yahoo.com   my parsonl yahoo Id and my addresh dhak of bangdash ct Narayongonj home bondor Rostompor Raylle Aybshick allaka 728/1Willson Rod bondor Narayongonj  my parsonl mobill contak Nambar :+8801819163317 im sobujmia use mobill nambr and same to Nambr im use Whapsafe nambr +8801819163317 sobujmia  and facebook i facebook add my hanilove_2**1*@yahoo.com  page sobumiahanilove and sobujmia 5/6page id im jast only for im use ok what 5/6 page im use bat my id cheting samthing mane hak bat im my skrat proses page and facebook id use not carat lok not my id sid ok.my oll in oll sid link world gmail id world of ol in onase sid im jast use ok 
       Bat Naxt my info my Raning ageo 42 yesr old im Maychut man sobujmia ok my 50%oll in oll paymnt my live home cantry im use posabol confom thes ok and naxt anetime my wapsid paymnt maythod and billing  and paypar and 3400pthujant my begnas and compnes job im Managar lunk online worlk sid compler oll time naxt my payment  send only for im use confo menetnsfar far my mobill nambr payment  caseh cod for bangdash bick Bank im out leglsh posabol ur paynt cash cod cash out back my hand ok +8801819163317 my mobill Nambr massage jasr pay in mobill nambr pay ok 
    ***** 

 engineering]], a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers), and ALU operations (which only occur between registers).[1]: 9–12 

RISC instruction set architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.[1]: 9–12 

For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.[1]: 9–12 

The earliest example of a load–store architecture was the CDC 6600.[1]: 54–56  Almost all vector processors (including many GPUs[2][better source needed]) use the load–store approach.[3]

See also

References

  1. ^ a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. ISBN 0867202041.
  2. ^ "AMD GCN reference" (PDF).
  3. ^ Harvey G. Cragon (1996). Memory systems and pipelined processors. pp. 512–513. ISBN 0867204745.


Stub icon

This computer-engineering-related article is a stub. You can help Wikipedia by expanding it.

Retrieved from "https://en.wikipedia.org/w/index.php?title=Load–store_architecture&oldid=994618598"