Quad Data Rate SRAM

Quad Data Rate (QDR) SRAM is a type of computer memory, more specifically a type of STATIC RAM, that can transfer four words of data in each clock cycle. Like Double Data-Rate (DDR) SDRAM, QDR SDRAM transfers data on both rising and falling edges of the clock signal.This requires a larger number of wires from the memory device to the memory controller, but doubles the theoretical maximum data transfer rate. QDR SRAM uses two clocks, one for read data and one for write data.

I/O

Clock Inputs

4 clock lines

• K
• not: /K
• C
• C not, /C

Control Inputs

2 control lines

• Write enable-not: /WPS
• Read enable-not: /RPS

Busses

one address bus and 2 data busses

• Address bus
• Data in bus
• Data out bus

Clocking Scheme

• Addresses
  • Read address latched on rising edge of K
  • Write address latched on rising edge of /K

• Data
  • Write
    • If /WPS is low
      • A data word on Data In is latched on rising edge of K
      • The next data word on Data In is latched on rising edge of /K
  • Read
    • A read is a two cycle process
    • If /RPS is low
      • The first rising edge of K latches the read address, A
      • The second rising edge of K puts the data word, from address A, on the Data Out bus
      • The next rising edge of /K puts the next data word, from address A+1, on the Data Out bus

External Links

• http://www.qdrsram.com
• Quad Data Rate SRAM Clocking Scheme Cypress
• Quad Data Rate Description Electronic design Artical