Resolution enhancement technologies
Resolution enhancement technologies are methods used to modify the photomasks in the lithographic processes used to make integrated circuits (ICs or "chips") to compensate for limitations in the optical resolution of the projection systems. These processes allow the creation of features well beyond the limit that would normally apply due to the Rayleigh criterion. Modern technologies allow the creation of features on the order of 5 nanometers (nm), far below the normal resolution possible using deep ultraviolet (DUV) light, which is about 400 nm wavelength.
Background
Integrated circuits are created in a multi-step process known as photolithography. This process starts with the design of the IC circuity as a series of layers than will be patterned onto the surface of a sheet of silicon or other semiconductor material known as a wafer.
Each layer of the ultimate design is patterned onto a photomask, which in modern systems is made of fine lines of chromium deposited on highly purified quartz glass. Chromium is used because it is highly opaque to UV light, and quartz because it has limited thermal expansion under the intense heat of the light sources as well as being highly transparent to ultraviolet light. The mask is positioned over the wafer and then exposed to an intense UV light source. The UV light drives chemical reactions is a thin layer of photoresist on the surface of the wafer, causing the photographic pattern to be physically recreated on the wafer.
Traditionally, after an IC design has been converted into a physical layout, the timing verified, and the polygons certified to be DRC-clean, the IC was ready for fabrication. The data files representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were shipped to the fab where they were used to repeatedly manufacture the designs in silicon. In the past, the creation of the IC layout was the end of the involvement of electronic design automation.
However, as Moore's law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now affecting the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped. These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types.
The first type is distortion corrections, namely pre-compensating for distortions inherent in the manufacturing process, be it from a processing step, such as: photolithography, etching, planarization, and deposition. These distortions are measured and a suitable model fitted, compensation is carried out usually using a rule or model based algorithm. When applied to printing distortions during photolithography, this distortion compensation is known as Optical Proximity Correction (OPC).
The second type of Reticle Enhancement involves actually improving the manufacturability or resolution of the process. Examples of this include:
| RET Technique | Manufacturability Improvement |
|---|---|
| Scattering Bars | Sub resolution assist features that improves the depth of focus of isolated features. |
| Phase-shift Mask | Etching quartz from certain areas of the mask (alt-PSM) or replacing Chrome with phase shifting Molybdenum Silicide layer (attenuated embedded PSM) to improve CD control and increase resolution |
| Double or Multiple Patterning | Involves decomposing the design across multiple masks to allow the printing of tighter pitches. |
For each of these manufacturability improvement techniques there are certain layouts that either cannot be improved or cause issues in printing. These are classed as non-compliant layouts. These are avoided either at the design stage - using, for instance, Radically Restrictive Design Rules and/or creating addition DRC checks if appropriate. Both the lithographic compensations and manufacturability improvements are usually grouped under the heading resolution enhancement techniques (RET). Such techniques have been used since the 180nm node and have become more aggressively used as minimum feature size as dropped significantly below that of the imaging wavelength, currently limited to 193 nm.
This is closely related to, and a part of, the more general category of design for manufacturability (IC) or DFM.
After RET, the next step in an EDA flow is usually mask data preparation.
See also
References
- Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, ISBN 0-8493-3096-3 A survey of the field, from which this summary was derived, with permission.