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Partial-response maximum-likelihood

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In computer data storage, partial-response maximum-likelihood (PRML) is a method for converting a weak analog signal from the head of a magnetic disk or tape drive into a digital signal. PRML attempts to correctly interpret even small changes in the analog signal, whereas peak detection relies on fixed thresholds. Because PRML can correctly decode a weaker signal, it allows higher density of data recording.

For example, PRML would read the magnetic flux density pattern "70, 60, 55, 60, 70" (where 60 is the baseline signal) as binary "101", and the same for "45, 40, 30, 40, 45" (baseline of 40), whereas a peak detector would decode everything above 50 (for example) as high, and below 50 as low, so the first pattern would read "111" and the second as "000".

In the presence of colored stationary and nonstationary data-dependent noise, the performance of the PRML detector can be improved by embedding a noise prediction/whitening process into the computation algorithm of the PRML detector. This noise-prediction-based sequence-estimation framework is known as noise-predictive maximum-likelihood detection (NPML).

Theoretical Development

Partial-response was first proposed by Adam Lender in 1963.[1] The method was generalized by Kretzmer in 1966. Kretzmer also classified the several different possible responses,[2] for example, PR1 is duobinary and PR4 is the response used in the classical PRML. In 1970, Kobayashi and Tang recognized the value of PR4 for the magnetic recording channel.[3]
Maximum-likelihood decoding using the eponymous Viterbi algorithm was proposed in 1967 by Andrew Viterbi as a means of decoding convolutional codes.[4]
By 1971, Hisashi Kobayashi at IBM had recognized that the Viterbi Algorithm could be applied to analog channels with inter-symbol interference and particularly to the use of PR4 in the context of Magnetic Recording[5] (later called PRML). (The wide range of applications of the Viterbi algorithm is well described in a review paper by Dave Forney.[6]) A simplified algorithm, based upon a difference metric, was used in the early implementations. This is due to Ferguson at Bell Labs.[7]

Implementation in Products

The first two implementations were in Tape (Ampex - 1984) and then in hard disk drives (IBM - 1990). Both are significant milestones with the Ampex implementation focused on very high data-rate for a digital instrumentation recorder and IBM focused on a high level of integration and low power consumption for a mass-market HDD. In both cases, the initial equalization to PR4 response was done with analog circuitry but the Viterbi algorithm was performed with digital logic. In the tape application, PRML superseded 'flat equalization'. In the HDD application, PRML superseded RLL codes with 'peak detection'.

Tape Recording

The first implementation of PRML was shipped in 1984 in the Ampex Digital Cassette Recording System (DCRS). The chief engineer on DCRS was Charles Coleman. The machine evolved from a 6-head, transverse-scan, digital video tape recorder. DCRS was a cassette-based, digital, instrumentation recorder capable of extended play times at very high data-rate.[8] It became Ampex' most successful digital product.[9]
The heads and the read/write channel ran at the (then) remarkably high data-rate of 117 Mbits/s.[10] The PRML electronics were implemented with four 4-bit, Plessey analog-to-digital converters (A/D) and 100k ECL logic.[11] Its mode of operation is best described in a paper by Wood and Petersen.[12] Petersen was granted a patent on the PRML channel but Ampex never took advantage of it.[13]

Hard Disk Drives (HDD)

In 1990, IBM shipped the first PRML channel in an HDD in the IBM 0681 (called Redwing during its development). The IBM 0681 was the last HDD product developed at the IBM Hursley, lab. in the UK. It was full-height 5¼-inch form-factor with up to 12 of 130 mm disks and had a maximum capacity of 857 MB.
The PRML channel for the IBM 0681 was developed in IBM Rochester lab. in Minnesota[14] with support from the IBM Zurich Research lab. in Switzerland[15]. A parallel R&D effort at IBM San Jose did not lead directly to a product[16].
The IBM 0681 read/write channel ran at a data-rate of 24 Mbits/s but was more highly integrated with the entire channel contained in a single 68-pin PLCC integrated circuit operating off a 5 volt supply. As well as the fixed analog equalizer, the channel boasted a simple adaptive digital 'cosine equalizer' after the A/D to compensate for changes in radius and/or changes in the magnetic components.

Write Precompensation

The presence of nonlinear transition-shift (NLTS) distortion on NRZ recording at high density and/or high data-rate was recognized in 1979[17]. The magnitude and sources of NLTS can be identified using the 'extracted dipulse' technique[18][19].
Ampex was the first to recognize the impact of NLTS on PR4[20]. and was first to implement Write precompensation for PRML NRZ recording. 'Precomp.' largely cancels the effect of NLTS. [21]. 'Precomp.'is viewed as a necessity for a PRML system and is important enough to appear in the BIOS HDD setup[22] although it is now handled automatically by the HDD.

Further Developments

Generalized PRML

PR4 is characterized by an equalization target (+1, 0, -1) in bit-response sample values or (1+D)(1-D) in polynomial notation (here, D is the delay operator referring to a one sample delay). The target (+1, +1, -1, -1) or (1+D)(1-D)^2 is called Extended PRML (or EPMRL). The entire family, (1+D)1-D)^n, was investigated by Thapar and Patel[23]. The targets with larger n value tend to be more suited to channels with poor high-frequency response. This series of targets all have integer sample values and form an open eye-pattern (e.g. PR4 forms a ternary eye). In general, however, the target can have non-integer values. The classical approach to maximum-likelihood detection on a channel with intersymbol interference (ISI) is to equalize to a minimum-phase, whitened, matched-filter target[24]. The complexity of the subsequent Viterbi detector increases exponentially with the target length - the number of states doubling for each 1-sample increase in target length.

Post-processor architecture

Given the rapid increase in complexity with longer targets, a post-processor architecture was proposed, firstly for EPRML[25]. With this approach a relatively simple detector (e.g. PRML) is followed by a post-processor which examines the residual waveform error and looks for the occurrence of likely bit pattern errors. This approach was found to be valuable when it was extended to systems employing a simple parity check[26]

PRML with Nonlinearities and Signal-dependent Noise

As data detectors became more sophisticated, it was found important to deal with any residual signal nonlinearities as well as pattern-dependent noise (noise tends to be largest when there is a magnetic transition between bits) including changes in noise-spectrum with data-pattern. To this end, the Viterbi-detector was modified such that it recognized the expected signal-level and expected noise variance associated with each bit-pattern. As a final step, the detectors were modified to include a 'noise predictor filter' thus allowing each pattern to havve a different noise=-spectrum. Such detectors are referred to as Pattern-Dependent Noise-Prediction (PDNP) detectors[27] or noise-predictive maximum-likelihood detectors (NPML)[28]

Recent Read/Write Electronics

Although the PRML acronym is still occasionally used, the most advanced detectors today (as of 2017) are around a million times more complex (gate-count) than the first PRML channel and operate about 100 times the data-rate (up to 3 Gbit/s). The analog front-end typically includes AGC, correction for the nonlinear read-element response, and a low-pass filter with control over the high-frequency boost or cut. Equalization is done after the A/D with a digital FIR equalizer. (TDMR uses a 2-input, 1-output equalizer.) The detector uses the PDNP/NPML approach but the hard-decision Viterbi algorithm is replaced with a detector providing soft-outputs (additional information about the reliability of each bit). Such detectors using a 'soft Viterbi algorithm' or BCJR algorithm are essential in iteratively decoding LDPC codes used in modern HDDs. A single integrated circuit contains the entire R/W channel (including the iterative decoder) as well as all the disk control and interface functions. There are two suppliers: Broadcom and Marvell[29].

See also

References

  1. ^ A. Lender, "The duobinary technique for high-speed data transmission", Trans. AIEE, Part I: Communication and Electronics, Vol. 82 , No. 2 , pp. 214-218, May 1963
  2. ^ E. Kretzmer, "Generalization of a Techinque for Binary Data Communication", IEEE Trans. Comm., Vol. 14, No. 1, pp. 67-68 Feb. 1966
  3. ^ H. Kobayashi and D. Tang, "Application of Partial-response Channel Coding to Magnetic Recording Systems", IBM J. Res. Dev., Vol, 14, No. 4, pp. 368-375, July 1970
  4. ^ A. Viterbi, "Error bounds for convolutional codes and an asymptotically optimum decoding algorithm", IEEE Trans. Info. Theory, Vol. 13, No. 2, pp. 260-269, Apr. 1967
  5. ^ H. Kobayashi, ”Correlative level coding and maximum-likelihood decoding", IEEE Trans. Inform. Theory, vol. IT-17, PP. 586-594, Sept. 1971
  6. ^ D. Forney, “The Viterbi Algorithm”, Proc. IEEE, Vol. 61, No. 3, pp. 268-278, Mar. 1973
  7. ^ M. Ferguson, ”Optimal reception for binary partial response channels” Bell Syst. Tech. J., vol. 51, pp. 493-505, Feb. 1972
  8. ^ T. Wood, "Ampex Digital Cassette Recording System (DCRS)", THIC meeting, Ellicott City, MD, 16 Oct., 1996 (PDF)
  9. ^ R. Wood, K. Hallamasek, "Overview of the prototype of the first commercial PRML channel", Computer History Museum, #102788145, Mar. 26, 2009
  10. ^ C. Coleman, D. Lindholm, D. Petersen, and R. Wood, "High Data Rate Magnetic Recording in a Single Channel", J. IERE, Vol., 55, No. 6, pp. 229-236, June 1985. (invited) (Charles Babbage Award for Best Paper)
  11. ^ Computer History Museum, #102741157, "Ampex PRML Prototype Circuit", circa 1982
  12. ^ R. Wood and D. Petersen, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Comm., Vol., COM-34, No. 5, pp. 454-461, May 1986 (invited)
  13. ^ D. Petersen, "Digital maximum likelihood detector for class IV partial response", US Patent 4504872, filed Feb. 8, 1983
  14. ^ J. Coker, R. Galbraith, G. Kerwin, J. Rae, P. Ziperovich, "Implementation of PRML in a rigid disk drive", IEEE Trans. Magn., Vol. 27, No. 6, pp. 4538-43, Nov. 1991
  15. ^ R.Cidecyan, F.Dolvio, R. Hermann, W.Hirt, W. Schott "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Comms, vol.10, No.1, pp.38-56, Jan 1992
  16. ^ T. Howell, et al. "Error Rate Performance of Experimental Gigabit per Square Inch Recording Components", IEEE Trans. Magn., Vol. 26, No. 5, pp. 2298-2302, 1990
  17. ^ R. Wood, R. Donaldson, "The Helical-Scan Magnetic Tape Recorder as a Digital Communication Channel", IEEE Trans. Mag. vol. MAG-15, no. 2, pp. 935-943, March 1979
  18. ^ D. Palmer, P. Ziperovich, R. Wood, T. Howell, "Identification of Nonlinear Write Effects Using Pseudo-Random Sequences", IEEE Trans. Magn., Vol. MAG-23, no. 5, pp. 2377-2379, Sept. 1987
  19. ^ D. Palmer, J. Hong, D. Stanek, R. Wood, "Characterization of the Read/Write Process for Magnetic Recording", IEEE Trans. Magn., Vol. MAG-31, No. 2, pp. 1071-1076, Mar. 1995 (invited)
  20. ^ P. Newby, R. Wood, "The Effects of Nonlinear Distortion on Class IV Partial Response", IEEE Trans. Magn., Vol. MAG-22, No. 5, pp. 1203-1205, Sept. 1986
  21. ^ R. Wood, S. Ahlgrim, K. Hallamasek, R. Stenerson, "An Experimental Eight-inch Disc Drive with One-hundred Megabytes Per Surface", IEEE Trans. Mag., vol. MAG-20, No. 5, pp. 698-702, Sept. 1984. (invited)
  22. ^ Kursk: BIOS Settings - Standard CMOS Setup, Feb 12, 2000
  23. ^ H.Thapar, A.Patel, "A Class of Partial Response Systems for Increasing Storage Density in Magnetic Recording", IEEE Trans. Magn., vol. 23, No. 5, pp.3666-3668 Sept. 1987
  24. ^ D. Forney, "Maximum Likelihood Sequence Estimation of Digital Sequences in the Presence of Intersymbol Interference", IEEE Trans. Info. Theory, vol. IT-18, pp. 363-378, May 1972.
  25. ^ R. Wood, "Turbo-PRML, A Compromise EPRML Detector", IEEE Trans. Magn., Vol. MAG-29, No. 6, pp. 4018-4020, Nov. 1993
  26. ^ M. Despotovic, V. Senk, "Data Detection", Chapter 32 in Coding and Signal Processing for Magnetic Recording Systems edited by B. Vasic, E. Kurtas, CRC Press 2004
  27. ^ J. Moon, J. Park, “Pattern-dependent noise prediction in signal dependent noise,” IEEE J. Sel. Areas Commun., vol. 19, no. 4, pp. 730–743, Apr. 2001
  28. ^ E. Eleftheriou, W. Hirt, "Improving Performance of PRML/EPRML through Noise Prediction". IEEE Trans. Magn. Vol. 32, No. 5, pp. 3968–3970, Sept. 1996
  29. ^ Marvell 88i9422 Soleil SATA HDD Controller., Sept 2015

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

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