Talk:Advanced Vector Extensions

Computing: Software C‑class Low‑importance

	This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.ComputingWikipedia:WikiProject ComputingTemplate:WikiProject ComputingComputing
C	This article has been rated as C-class on Wikipedia's content assessment scale.
Low	This article has been rated as Low-importance on the project's importance scale.
	This article is supported by WikiProject Software (assessed as Low-importance).
	This article is supported by Computer hardware task force (assessed as Low-importance).

Introduction

Intro doesn't tell the story of what AVX is supposed to do, as in its purpose. Intro refers vaguely to "new features".

AVX-512

The section on AVX-512 looks like it has been copied from a news release. Maybe it should be a separate article. It needs to point out the distinction between the unnamed instruction set of Knights Corner and the AVX-512 instruction set of Knights Landing. The former uses an MVEX prefix and the latter uses an EVEX prefix. These two prefixes differ by a single bit, even for otherwise identical instructions. Therefore the two instruction sets are not mutually compatible, but both are backwards compatible with AVX2. Does anybody have info about the fate of the Knights Corner instruction set? Is it obsolete or will both lines be continued? Afog 09:48, 2 October 2013 (UTC)[reply]

Completely rewritten

I have rewritten the whole page to fix the issues discussed below and because the article had the tag:

AES, PCLMUL and FMA are separate instruction sets which I have put into separate articles. I have added information about AMD support, operating system support and many technical details. Afog (talk) 11:50, 4 June 2009 (UTC)[reply]

extended precision?

I want to clarify that AVE does 4x64 bit (double precision) and 8x32 bit (single precision) but NOT 2x128 (extended precision). The docs seem to indicate this as there is nothing mentioned about 128 bit floating point numbers. Can an expert please verify this statement as it is critical to understanding AVE.

Gene Thomas (talk) 03:08, 22 May 2009 (UTC)[reply]

Note: Extended double precision is 80 bits in size, but is often stored as 128-bit for alignment. True 128-bit floating point numbers are "quadruple precision". I have no idea if AVX supports either of these things. Aaronfranke (talk) 19:40, 18 September 2019 (UTC)[reply]

why does AVX look like altivec?

ibm calls AltiVec VMX, and actually never believed in altivec before apple and nintendo insisted on it for the Gecko and the later G5 design upgraded on the G5 to a 256bit SIMD and a 128Bit SIMD on the Gamecube and Wii. personally i think apple might have had something to do with AVX, but that's just speculation Markthemac (talk) 01:45, 9 June 2008 (UTC)[reply]

FMA

The article states that 1) the published AVX instruction set includes FMA instructions, and 2) FMA will appear in a future extension of the instruction set. There's a contradiction here, please clarify. --85.140.239.250 (talk) 20:22, 5 December 2008 (UTC)[reply]

Power efficient, idle power usage is insignificant

This is supposedly due to the new instructions? I think a link to source material is needed here or atleast a re-write, as generally I understand the term idle to imply that the processor is doing nothing! As I understand it, power usage during idle NOP instructions is a function of the power control unit within the CPU and not due to an instruction which in an Intel cpu is a microcode op or series of microcode ops.

I would suggest that the meaning here is to imply that a future CPU implementing AVE will have enhanced power control over these new instructions, shutting off unused units during AVE instuction execution. —Preceding unsigned comment added by 86.13.171.234 (talk) 00:16, 10 January 2009 (UTC)[reply]

The phrase "idle power usage is insignificant" refers to the power usage caused by leakage current of the extra transistors added to implement the AVX logic in the processor. Transistors use power even when they are not switching. All modern x86 processors shutoff idle units by gating the clock signal into the unit. When the clock signal is turned off, power consumption of the unit will be due solely to transistor leakage current. The power consumed by the AVX unit when the AVX unit is idle is an insignificant portion of the total power consumed by the processor. Typically, this would mean below 1% of total power. Ksavage9 (talk) 20:50, 20 April 2009 (UTC)[reply]

AMD reaction

Please incorporate in article info from http://forums.amd.com/devblog/blogpost.cfm?catid=208&threadid=112934 —Preceding unsigned comment added by 83.167.112.66 (talk) 14:11, 6 May 2009 (UTC)[reply]

Compiler support

Free Pascal is developing support for AVX within their SVN repository. I don't know if that's applicable or not to mention. PrincessSchala (talk) 08:09, 14 March 2012 (UTC)[reply]

three-operand instruction for sqrt?

Maybe someone can explain what sqrt with 3 operands means? xmm1=xmm2=sqrt(xmm3)?

 vsqrtsd xmm1, xmm2, xmm3

I'm disappointed - no fast exp(), cos() etc. Unlike CUDA. Intel really has a problem. Oh, and have to get a new operating system to use the thing. Oh, really. — Preceding unsigned comment added by 113.190.231.252 (talk) 11:51, 21 July 2012 (UTC)[reply]

Windows XP and AVX

Does Windows XP support the AVX instructions? If not, what is the minimum Microsoft OS needed to support AVX? — Preceding unsigned comment added by 222.165.42.62 (talk) 10:49, 25 October 2012 (UTC)[reply]

Windows XP does not support AVX for the obvious reason that it is 32-bit. To use modern features of 64-bit processors, you need to use a 64-bit operating system made for 64-bit processors. Windows 7 64-bit supports AVX, but only with Service Pack 1. Aaronfranke (talk) 19:47, 18 September 2019 (UTC)[reply]

AVX the successor to SSE?

Would it be correct to call AVX the successor to SSE (more precisely SSE4)? — Preceding unsigned comment added by 222.165.42.62 (talk) 04:01, 30 October 2012 (UTC)[reply]

Split off AVX-512

I plan to split AVX-512 off to a separate article. The EVEX based AVX-512 has many new details and consists of several new separate extensions, so it will be better dealt with separately. This can leave this article to deal with 128/256-bit VEX encoded AVX extensions. Any comments or objections? Carewolf (talk) 20:18, 23 February 2014 (UTC)[reply]

If you ask me, go ahead. — Dsimic (talk | contribs) 23:11, 23 February 2014 (UTC)[reply]

Knights Landing out date

"Knights Landing processor scheduled to ship in 2015"

The reference provided for this sentence doesn't talk about the shipping date. I couldn't find this date yet on the Internet. — Preceding unsigned comment added by 2A00:FE00:4103:1:0:0:0:300 (talk) 08:28, 22 August 2014 (UTC)[reply]

I've resolved this issue. Aaronfranke (talk) 19:48, 18 September 2019 (UTC)[reply]

AVX-128

This article states that it's safe to use AVX-128 on OSes that support only SSE and don't support AVX.

In Intel(R) Advanced Vector Extensions Programming Reference or Intel® Architecture Instruction Set Extensions Programming Reference, section "3.2: YMM STATE MANAGEMENT" it is clearly stated that

"An OS must enable its YMM state management to support AVX and FMA extensions. Otherwise, an attempt to execute an instruction in AVX or FMA extensions (including an enhanced 128-bit SIMD instructions using VEX encoding) will cause a #UD exception."

Also, according to AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions even 128-bit XOP also cause #UD exception if an OS doesn't support YMM save/restore.

So I believe that the statement that "AVX-128 instructions that do not use YMM registers are also safe to use on operating systems without AVX-support[citation needed], since AVX-support in operating systems refers to handling YMM register state.[3]" is totally incorrect. — Preceding unsigned comment added by 109.188.120.144 (talk) 00:46, 25 October 2015 (UTC)[reply]

P.S. it makes sense, since AVX-128 instructions clear the upper half of a destination YMM register, so even AVX-128 touches all 256 bits of YMM reg. — Preceding unsigned comment added by 109.188.120.144 (talk) 09:22, 25 October 2015 (UTC)[reply]

It lacks a citation anyway, so feel free to remove it. I think it was based on the 128-bit forms doesn't use YMM registers.Carewolf (talk) 09:19, 26 October 2015 (UTC)[reply]