make (software)
In computer programming, make is a utility for automatically building large applications. Files specifying instructions for make are called Makefiles. make is most commonly used in C/C++ projects, but in principle it can be used with almost any compiled language.
The basic tool for building an application from source code is the compiler. make is a separate, higher-level utility which tells the compiler which source code files to process. It tracks which ones have changed since the last time the project was built and invokes the compiler on only the components that depend on those files. Although in principle one could always just write a simple shell script to recompile everything at every build, in large projects this would consume a prohibitive amount of time. Thus, a makefile can be seen as a kind of advanced shell script which tracks dependencies instead of following a fixed sequence of steps.
Today, programmers increasingly rely on Integrated Development Environments and language-specific compiler features to manage the build process for them instead of manually specifying dependencies in makefiles. However, make remains widely used, especially in Unix-based platforms.
Origin
There are now a number of dependency-tracking build utilities, but make is one of the most wide-spread, primarily due to its inclusion in Unix, starting with the PWB/UNIX 1.0, which featured a variety of tools targeting software development workloads. It was originally created by Stuart Feldman in 1977 at Bell Labs. In 2003 Dr. Feldman received the ACM Software System Award for the invention of this important tool.
Before make's introduction, the Unix build system would most likely consist of "make" and "install" shell scripts accompanying a program's source. Being able to combine the commands for the different targets into a single file, and being able to abstract out dependency tracking and archive handling, was an important step in the direction of modern build environments.
Modern versions
Make has gone through a number of rewrites, and a number of from-scratch variants which used the same file format and basic algorithmic principles, and also provided a number of their own non-standard enhancements, in the time that followed. Some of them are:
- BSD make, which is derived from Adam de Boor's work on a version of make capable of building targets in parallel, and survives with varying degrees of modification in FreeBSD, NetBSD and OpenBSD. Most notably, it has conditionals and iterative loops which are applied at the parsing stage and may be used to conditionally, and programmatically, construct the makefile, including generation of targets at runtime.
- GNU make, which is part of most GNU/Linux installations and is frequently used in conjunction with the GNU build system. Its notable departures from traditional make are most noticeable in pattern-matching in dependency graphs and build targets, as well as a number of functions which may be invoked to have the make utility do things like collect a list of all files in the current directory. Where BSD make has a rich set of internal macros at parse time, GNU make typically encourages the use of an external macro package like m4.
- Microsoft nmake, commonly available on Windows. It is fairly basic, offering only a subset of the features of the two above makes. Note that there exists another, incompatible program also called nmake from AT&T for Unix.
POSIX includes standardization of the basic features and operation of the make utility, and is implemented with varying degrees of completeness in Unix-based versions of make. In general, simple makefiles may be used between various versions of make with reasonable success. Some versions of GNU make and BSD make will look first for files named "GNUmakefile" and "BSDmakefile" respectively, which allows one to put makefiles which use implementation-defined behaviour in separate locations.
Advantages and disadvantages
Like most software which has been around for as long as make has, it has its share of fans and detractors. Many problems have surfaced with scaling make to work with modern, large software projects, some contend, but many also point out that for the common case, make works very well, and has very simple, but powerful, expressiveness. In any event, make is still used for building many complete operating systems, and modern replacements are not very different in their basic operation.
One disadvantage is that make is non-linear language and difficult for software developers used to using a linear/sequential language to follow. An additional disadvantage is the lack of tools to debug and single step through a makefile to diagnose problems.
With the advent of modern Integrated Development Environments, especially on non-Unix platforms, many programmers do not manually manage dependency tracking, or even the listing of which files are part of a project, and instead leave that task to be automated by their environment. Likewise, many modern programming languages have language-specific ways of listing dependencies which are more efficiently tracked through the use of language-specific build utilities.
Makefile structure
A makefile consists of lines of text which define a file (or set of files) or a rule name as depending on a set of files. Output files are marked as depending on their source files, for example, and source files are marked as depending on files which they include internally. After each dependency is listed, a series of lines of tab-indented text may follow which define how to transform the input into the output, if the former has been modified more recently than the latter. In the case where such definitions are present, they are referred to as "build scripts" and are passed to the shell to generate the target file. The basic structure is:
# Comments use the pound sign (aka hash) target: dependencies command 1 command 2 . . . command n
A makefile also can contain definitions of variables and inclusion of other makefiles. Variables in makefiles may be overridden in the command line arguments passed to the make utility. This allows users to specify different behaviour for the build scripts and how to invoke programs, among other things. For example, the variable "CC" is frequently used in makefiles to refer to a C compiler, and the user may wish to provide an alternate compiler to use.
Example makefile
Below is a very simple makefile that would compile a source called "helloworld.c" using cc, a C compiler. The PHONY tag is a technicality that tells make that a particular target name does not produce an actual file. The $@ and $< are two of the so-called automatic variables and stand for the target name and so-called "implicit" source, respectively. There are a number of other automatic variables.
helloworld: helloworld.o
cc -o $@ $<
helloworld.o: helloworld.c
cc -c -o $@ $<
.PHONY: clean
clean:
rm -f helloworld helloworld.o
Debugging Makefiles
Make debugging involves two main methods:
- Tracing makefile execution using a command line argument to make
- Adding debug print statements to each build rule using 'echo'
John Graham-Cumming has written a series of aritcles on GNU Make debugging including Makefile Debugging: Tracing Macro Values, An Interactive GNU Make Debugger, Dynamic Breakpoints in the GNU Make Debugger, Tracing Rule Execution in GNU Make and Printing the value of a Makefile variable. There is also the GNU Make Debugger open source project [1].
Similar tools
There are also many tools which are like make, but which are not compatible with its makefile format. A comprehensive list is available on the A-A-P website. Some of the most notable are listed at the article on Build Automation.