Intel 5-level paging
Intel 5-level paging, referred to simply as 5-level paging in Intel documents, is an upcoming processor extension for the x86-64 line of processors.[1] It extends the virtual address space from 48 bits to 57 bits, increasing the addressable virtual memory from 256 terabytes to 128 petabytes. While official the technical document describing the extension is still a white paper, stating "do not finalize a design with this information", support for the extensions has already been implemented in the linux kernel.[2]
References
- ^ 5-Level Paging and 5-Level EPT (PDF). Intel Corporation. 2017.
- ^ Tung, Liam. "First Linux 4.14 release adds "very core" features, arrives in time for kernel's 26th birthday | ZDNet". ZDNet. Retrieved 2018-04-25.