Address decoder

in digital electronics, an Address decoder is a circuit that has two or more bits of an address bus as inputs and that has one or more device selection lines as outputs. When the address for a particular device appears on the address bus, the address decoder asserts the selection line for that device. A separate single-device address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices. In the latter case, an address decoder with N address input bits can serve up to 2^N separate deivces. A classic example is the 74154 integrated circuit. This address decoder has four address inputs and sixteen (i.e., 2⁴ ) device selector outputs. An address decoder is also referred to as a "demultiplexor" or "demux," although these terms are more general and can refer to devices other than address decoders. The 74154 mentined above can be called a "4-to-16 demux."

Address decoders are fundamental building blocks for systems that use busses. They are represented in all integrated circuit families and processes and in all standard FPGA and ASIC libraries. They are discussed in introductory texbooks in digital logic design.