Wikipedia:Cleanup Taskforce/Front side bus

Front Side Bus

The article asserts:

For example, the current Core 2 architecture seems to perform better at a 1:1 ratio (that is, FSB1066 - true 266 MHz * quad-pumping - and DDR2-533 - true 266 MHz * double pumping) than a 4:5 ratio (using DDR2-667), but stepping it up to a 2:3 ratio (DDR2-800) or higher seems to increase performance over a 1:1 ratio.

Although no justification or reference is provided.

All-in-all the FSB topic is very important and this article really needs to be rewritten by someone with a deep technical understanding of processors and chip sets, and practical experience in overclocking.