Intel microcode
Intel Microcode runs inside x86 processors made by Intel. Since the P6 microarchitecture introduced in the mid-1990s, the microcode programs can be patched by the operating system or BIOS firmware to workaround bugs found in the CPU after release.
Micro-operations have a consistent format with up to three source inputs, and two destination outputs.[1] The processor performs register renaming to map these inputs to and from the real register file (RRF) before and after their their execution.[1] Out-of-order execution is used, so the micro-operations and instructions they represent may not appear in the same order.
References
- ^ a b Ronen, Ronny (18 January 2005). Micro Operations (Uops) (PDF). The Pentium II/III Processor "Compiler on a Chip" (Report). Tel Aviv University. pp. 26, 31, 32, 43, 44, 46. Archived from the original (PDF) on 16 April 2007. Retrieved 23 January 2018.
Each "CISC" inst is broken into one or more uops … Canonical representation of src/dest (3 src, 2 dest) … e.g.,
pop eaxbecomesesp1<-esp0+4, eax1<-[esp0]… ID: Convert instructions into uops. Buffers up to 6 uops … Alloc & RAT … able to work on up to 3 uops per clock … Reservation station (RS) … Pool of all "not yet executed" uops (up to 20) … In order Retirement: … Retires up to 3 uops per clock … OOO Cluster … Up to 5 resource-ready uops are selected, and dispatched per clock