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List of Intel CPU microarchitectures

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The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model.

x86 microarchitectures

Year Microarchitecture Pipeline stages max. Clock
1989 486 (80486) 3 100 MHz
1993 P5 (Pentium) 5 300 MHz
1995 P6 (Pentium Pro; later Pentium II) 14 (17 with load & store/retire)
[further explanation needed] 		450 MHz
1999 P6 (Pentium III) 12 (15 with load & store/retire) 450–1400 MHz
2000 NetBurst (Pentium 4) 20 unified with branch prediction 800–3466 MHz
2003 Pentium M 10 (12 with fetch/retire)
[further explanation needed] 		400–2133 MHz
2004 Prescott 31 unified with branch prediction 4000 MHz
2006 Intel Core 12 (14 with fetch/retire) 3333 MHz
2008 Nehalem 20 unified (14 without miss prediction) 3600 MHz
2008 Bonnell 16 (20 with prediction miss) 2100 MHz
2011 Sandy Bridge 14 (16 with fetch/retire) 4000 MHz
2013 Silvermont 14-17 (16-19 with fetch/retire) 2670 MHz
2013 Haswell 14 (16 with fetch/retire) 4400 MHz
2015 Skylake 14 (16 with fetch/retire) 4200 MHz
2016 Goldmont 20 unified with branch prediction 3500 MHz
2016 Kaby Lake 14 (16 with fetch/retire) 4500 MHz
2017 Cannonlake 14 5000 MHz
Before P5
  • 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
  • 186: included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions.
  • 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086. Included instructions relating to protected mode.
  • i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
  • i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
P5
original Pentium microprocessors, first x86 processor with super scaling feature, branch prediction and RISC µop decode scheme.
P6
used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)".
NetBurst
Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural upgrade. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to protect pages containing code by marking them as read-only, for security purposes.
Pentium M
updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
Intel Core
reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
Nehalem
released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
Bonnell
45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
Larrabee (cancelled 2010)
multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
Sandy Bridge
released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
Silvermont
22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
Haswell
22 nm microarchitecture, released June 3, 2013. Added a number of important powerful new instructions, including FMA.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
Skylake
new 14 nm microarchitecture, released August 5, 2015.
  • Goldmont: 14 nm Atom microarchitecture, borrows heavily from Skylake processors, released April 2016.[2][3]
  • Kaby Lake: successor to Skylake, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
  • Coffee Lake: successor to Kaby Lake and a second refinement to the 14 nm process
  • Cannonlake: expected in late 2017. It will be a 10 nm shrink of Kaby Lake. Formerly called Skymont.
Ice Lake
new 10 nm microarchitecture, expected in 2018.
  • Tiger Lake: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.

Itanium microarchitectures

Merced microarchitecture
original Itanium microarchitecture. Used only in the first Itanium microprocessors.
McKinley microarchitecture
enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
Montecito microarchitecture
enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
Tukwila microarchitecture
enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
Poulson microarchitecture
Itanium processor featuring a new microarchitecture.[4]
Kittson microarchitecture
future Itanium processors

Roadmap

Pentium 4 / Core Roadmap
Architectural
change 		Fabri-
cation
process 		Micro-
archi-
tecture 		Code
names 		Release
date 		Processors
8P/4P
Server 		4P/2P
Server/WS 		Enthusiast/
WS 		Desktop Mobile
Tick
(New fab. process) 		180 nm P6,
NetBurst 		Willamette 2000-11-20
Tick
(New fab. process) 		130 nm Northwood/
Mobile Pentium 4 		2002-01-??
Tick
(New fab. process) 		90 nm Prescott 2004-02-01
Tick
(New fab. process) 		65 nm Presler,
Cedar Mill,
Yonah 		2006-01-05 Presler Cedar Mill Yonah
Tock
(New micro-
architecture) 		Core Merom[5] 2006-07-27
[6] 		Tigerton Woodcrest
Clovertown 		Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11
[7] 		Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 2008-11-17
[8] 		Beckton Gainestown Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 2010-01-04
[9][10] 		Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy
Bridge 		Sandy Bridge
(2nd Gen) 		2011-01-09
[11] 		–[12] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[13] Ivy Bridge
(3rd Gen) 		2012-04-29 Ivy Bridge-EX
[14] 		Ivy Bridge-EP
[14] 		Ivy Bridge-E
[15] 		Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell
(4th Gen) 		2013-06-02 Haswell-EX Haswell-EP Haswell-E Haswell-DT
[16] 		Haswell-MB (37–57W TDP, PGA package)
Haswell-H (47W TDP, BGA package)
Haswell-ULP/ULX (11.5–15W TDP)[16]
Optimizations
(Fabrication process/
microarchitecture
improvements) 		Devil's
Canyon[17] 		2014-06 – – – Haswell-DT –
Tick 14 nm[13] Broadwell
(5th Gen)[18] 		2014-09-05 Broadwell-EX
[19] 		Broadwell-EP
[19] 		Broadwell-E Broadwell-DT Broadwell-H (37–47W TDP)
Broadwell-U (15–28W TDP)
Broadwell-Y (4.5W TDP)
Tock Skylake[18] Skylake
(6th Gen)[18] 		2015-08-05
[20] 		Skylake-EX Skylake-SP
(formerly
Skylake-EP) [21] 		Skylake-X [22] Skylake-S Skylake-H (35–45W TDP)
Skylake-U (15–28W TDP)
Skylake-Y (4.5W TDP)
Optimizations
[23][24][25][26] 		Kaby Lake
(7th Gen)[27] 		2017-01-03
[28] 		Kaby Lake-X
[29] 		Kaby Lake-S Kaby Lake-H (35–45W TDP)
Kaby Lake-U (15–28W TDP)
Kaby Lake-Y (4.5W TDP)
Kaby Lake
Refresh
(8th Gen) 		2017-09
Coffee Lake 2018-02
[30]
Tick 10 nm[31] Cannonlake 2H 2017
[27]
Tock Ice
Lake[26] 		Ice Lake[32] 2018
Optimization[26] Tigerlake[26] 2019
Tick 7 nm[31]
Tock
Optimization
Tick 5 nm[31]
Tock
Optimization

Atom Roadmap[33]
Fabri-
cation
process 		Micro-
archi-
tecture 		Release
date 		Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
Tick 45 nm Bonnell 2008 Silverthorne — Diamondville Tunnel Creek,
Stellarton 		— Sodaville
Tock 2010 Lincroft Pineview Groveland
Tick 32 nm Saltwell 2011 Medfield (Penwell & Lexington),
Clover Trail+ (Cloverview) 		Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
Tick 22 nm Silvermont 2013 Merrifield (Tangier) [34], Slayton,
Moorefield (Anniedale)[35] 		Bay Trail-T
(Valleyview) 		Bay Trail-M
(Valleyview) 		Bay Trail-D
(Valleyview) 		Bay Trail-I
(Valleyview) 		Avoton Rangeley Un­known
Tick 14 nm[33] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) [36] Braswell [37] Denverton Cancelled Un­known Un­known
Tock Goldmont[38] 2016 Broxton Cancelled Willow Trail Cancelled
Apollo Lake 		Apollo Lake [39] Denverton [40] Un­known Un­known
Optimization Goldmont
Plus[41] 		2017 Un­known Un­known Gemini Lake Un­known Un­known Un­known
Tick 10 nm Un­known 2018 Un­known Un­known Mercury Lake Un­known Un­known Un­known

See also

References

  1. ^ "An Update On Our Graphics-related Programs". May 25, 2010.
  2. ^ "Intel Software Development Emulator".
  3. ^ ""Goldmont"- the sequel to Silvermont Atom?".
  4. ^ Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Retrieved 2007-10-05.
  5. ^ Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
  6. ^ Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing, Intel Unveils World's Best Processor
  7. ^ Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology
  8. ^ Intel Launches Fastest Processor on the Planet
  9. ^ http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf
  10. ^ Revolutionizing How We Use Technology—Today and Beyond
  11. ^ Intel Sandy Bridge chip coming January 5
  12. ^ Intel Ivy Bridge CPU Range Complete by Next Year
  13. ^ a b 22nm technology. May 2011
  14. ^ a b http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html
  15. ^ Ivy Bridge-E Delayed Until Second Half of 2013
  16. ^ a b "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25.
  17. ^ "Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel". golem.de. Jun 3, 2014.
  18. ^ a b c After Intel's Haswell comes Broadwell - SemiAccurate
  19. ^ a b Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015
  20. ^ The wait for Skylake is almost over, first desktop chips likely to hit August 5
  21. ^ Windeck, Christof. "Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"". heise.de. Retrieved 2 May 2017.
  22. ^ Mujtaba, Hassan. "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". wccftech.com. Retrieved 2 May 2017.
  23. ^ "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'". Anandtech. Retrieved 23 March 2016.
  24. ^ "Intel 14nm Kaby Lake "Skylake Refresh" Platform Detailed – Launching in 2H 2016, 256 MB eDRAM H-Series and 91W K-Series Unveiled". wccftech.com. July 2015. The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher
  25. ^ "Intel Releasing 14nm Kaby Lake Processor in 2016 Ahead of 10nm Cannonlake". legitreviews.com. 2015-07-08. We have long known that Intel was planning a 'Skylake Refresh' that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.
  26. ^ a b c d "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20.
  27. ^ a b "Intel confirms tick-tock shattering Kaby Lake processor as Moore's Law falters". ArsTechnica.com. Jul 15, 2015. the switch to 10nm manufacturing has been delayed until the second half of 2017.
  28. ^ https://arstechnica.com/gadgets/2017/01/intel-pushes-out-the-rest-of-its-kaby-lake-processors-for-2017s-pcs/
  29. ^ Mujtaba, Hassan. "Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June". wccftech.com. Retrieved 2 May 2017.
  30. ^ https://www.golem.de/news/cpu-roadmap-kaby-lake-r-im-september-2017-coffee-lake-im-februar-2018-1706-128176.html
  31. ^ a b c "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25.
  32. ^ http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx
  33. ^ a b "Intel's Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
  34. ^ Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress.
  35. ^ "Import Data and Price of anniedale".
  36. ^ "アウトオブオーダーと最新プロセスを採用する今後のAtom".
  37. ^ "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016.
  38. ^ Smith, Ryan; Cutress, Ian (29 April 2016). "Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled". Anandtech.com. Retrieved 29 June 2016.
  39. ^ "Products (Formerly Apollo Lake)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
  40. ^ "Products (Formerly Denverton)". Intel® ARK (Product Specs). Retrieved 6 January 2016.
  41. ^ Wan, Samuel (2 June 2017). "Intel Gemini Lake SoC Leaked and Detailed". eTeknix.com. Retrieved 2 June 2017.
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