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The claim in the article that imprecise exceptions cannot occur except in Out-Of-Order machines is wrong: in an in-order pipelined, single or superscalar machine there may be multiple simultaneous exceptions. Not every exception is detected at the same pipeline stage, and some late exceptions like bus errors may be detected only after subsequent instructions have completed. Where certain instructions are dispatched to a coprocessor, as in 80287 or MC68881, they may signal exceptions asynchronously! — Preceding unsigned comment added by 173.48.253.79 (talk) 11:05, 28 March 2015 (UTC)[reply]
