Talk:Predication (computer architecture)

Unnamed section

The binary GCD algorithm in ARM assembly is probably appropriate on this page (but not on the page it references). I'm not sure how I copy the code from the latest page that had the code: http://en.wikipedia.org/w/index.php?title=Binary_GCD_algorithm&oldid=468833079 — Preceding unsigned comment added by 130.208.138.229 (talk) 20:33, 27 March 2013 (UTC)

There is a problem with the first sentence,

"Because computer programs respond to a user, there is no way around the fact that portions of a program need to be executed conditionally."

A program which computes a formula from user input may not need to branch, and conversely a program with complex logic which receives no direct inputs from a user (paging in the OS) may need to branch.

It is unclear exactly how to introduce this topic. Mjr1007 (talk) 17:24, 29 July 2008 (UTC)

Correct Term?

I would like to ask whether this article should not be called "branch prediction". This term seems to be used more frequently The reverse term "misprediction" seems to be uncontested Semantically, "branch predication" seems to be something related to a predicate rather than to prediction.

— Preceding unsigned comment added by 141.3.24.54 (talk) 07:30, 22 April 2014 (UTC)

It should not be called "branch prediction". As the hatnote in the article says, branch predication is not to be confused with a branch predictor; it should also not be confused with what a branch predictor does, namely branch prediction. So, yes, "branch predication" is something related to a predicate rather than to prediction, which is why this article is called "branch predication", not "branch prediction".

"Branch prediction" is used more frequently than "branch predication" or just "predication" because branch prediction is done more frequently than predication - most general-purpose processors, and many embedded processors, do branch prediction, but only some instruction sets have predicated non-branch instructions, and, for x86, at least, most instructions aren't predicated.

I'm not sure why this article's title is "branch predication"; the instructions that are typically made conditional are non-branch instructions, such as moves (in the case of x86's CMOVE, as introduced in, as I remember, the Pentium Pro) or other non-branch instructions (as on 32-bit ARM). Guy Harris (talk) 09:48, 22 April 2014 (UTC)

It's called "branch predication" as predication actually substitutes the branches used for conditional execution. So, it's like "predicating branches" or something like that, what leads to "branch predication". — Dsimic (talk | contribs) 20:43, 22 April 2014 (UTC)

I agree that the topic discussed in this article is different from the topic discussed in the branch predictor article, and so they should not be merged. However, I am just as mystified as Guy Harris as to why this article is titled "branch predication". My understanding is that the topic discussed in this article is far more commonly called "conditional execution", as in the ARM architecture#Conditional execution, addressing mode#Conditional execution, FX8010, EVEX prefix, Electrologica X1, etc. articles. So I suggest moving this article to "conditional execution" or "conditional instruction". --DavidCary (talk) 17:11, 10 December 2015 (UTC)

The difference is:

One article talks about extra hardware used on some processors to guess (predict) ahead of time which way a conditional branch instruction will go, and speculatively execute a few instructions past that point, and then later after the branch condition has resolved to either accept or cancel those speculatively-executed instructions. That hardware ignores non-branch instructions. That kind of hardware in the microarchitecture could be used to speed up any instruction set.

The other article talks about a feature of a few instruction sets -- such instruction sets such that every instruction (not only branch instructions) is conditional. That feature of a instruction set architecture can speed up the execution of certain programs, but it does not apply to most instruction sets. --DavidCary (talk) 06:17, 15 December 2015 (UTC)

Additional advantage

According to the Intel® Itanium® Architecture Software Developer’s Manual Volume 1: Application Architecture

http://download.intel.com/design/Itanium/manuals/24531705.pdf

In section 4.2.4.1

This code takes 18 cycles to complete if p2 is true and five cycles if p2 is false. When analyzing such cases, consider execution weights, branch misprediction probabilities, and prediction costs along each path.

The execution times decreases if the predicate is false.

Mjr1007 (talk) 18:16, 29 July 2008 (UTC)

This is also important for SIMD. It might be better to fill execution units with data not to be processed than to realign and reschedule. Mathematically speaking not branching around multiplying with one or adding zero. --Moritzgedig (talk) 11:27, 28 November 2014 (UTC)