Jump to content

Electronic system-level design and verification

Edit links
From Wikipedia, the free encyclopedia
This is an old revision of this page, as edited by Minnesotasteve (talk | contribs) at 17:38, 17 February 2017. The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Electronic system level (ESL) design and verification is an emerging electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, an EDA-industry-analysis firm, on February 1, 2001.[1] It is defined in ESL Design and Verification [2] as: "the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner."

The basic premise is to model the behavior of the entire system using a high-level language such as C, C++, LabVIEW, or MATLAB or using graphical "model-based" design tools. Newer languages are emerging that enable the creation of a model at a higher level of abstraction including general purpose system design languages like SysML as well as those that are specific to embedded system design like SMDL and SSDL. Rapid and correct-by-construction implementation of the system can be automated using EDA tools such as high-level synthesis and embedded software tools, although much of it is performed manually today. ESL can also be accomplished through the use of SystemC as an abstract modeling language.

Electronic System Level is an established approach at many of the world’s leading System-on-a-chip (SoC) design companies, and is being used increasingly in system design.[3] From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification, and debugging through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on board, and entire multi-board systems.

See also

References

  1. ^ Information and results for 'System-level design merits a closer look: the complexity of today's designs requires system-level. However, EDA-tools development is lagging behind the needs of semiconductor and systems companies, and EDA tools must provide support.(Cover Story)' | AccessMyLibrary - Promoting library advocacy. AccessMyLibrary. Retrieved on 2013-08-10.
  2. ^ Brian Bailey, Grant Martin and Andrew Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology. Morgan Kaufmann/Elsevier, 2007.
  3. ^ Adamov, Alexander. "Electronic System Level Models for Functional Verification of System-on-Chip". CAD Systems in Microelectronics.

Further reading

  • Alice C. Parker; Yosef Tirat-Gefen; Suhrid A. Wadekar (2007). "System-Level Design". In Wai-Kai Chen (ed.). The VLSI handbook (2nd ed.). CRC Press. ISBN 978-0-8493-4199-1. chapter 76.
  • Brian Bailey; Grant Martin (2010). ESL Models and Their Application: Electronic System Level Design and Verification in Practice. Springer. ISBN 978-1-4419-0964-0.
  • Frank Rogin; Rolf Drechsler (2010). Debugging at the Electronic System Level. Springer. ISBN 978-90-481-9254-0.
  • Liming Xiu (2007). VLSI circuit design methodology demystified: a conceptual taxonomy. Wiley-IEEE. ISBN 978-0-470-12742-1.
Retrieved from "https://en.wikipedia.org/w/index.php?title=Electronic_system-level_design_and_verification&oldid=766004315"