Asynchronous array of simple processors
AsAP is a low-power DSP chip-multiprocessor designed by the VLSI Computation Labratory (VCL) at the University of California, Davis. Version 1.0 was designed in 0.18 μm CMOS technology and was fabricated during the summer of 2005. Early testing in the fall of 2005 showed it to be fully functional. To the best of the research groups knowledge, it is the highest clock rate fabricated processor designed by a university.
Key Features
AsAP uses a chip multi-processor architecture to achieve high performance. It uses small memories and a simple architecture in each processor to provide high energy efficiency as well as a globally asynchronous locally synchronous clocking style (called GALS) to simplify the clock design. It also uses nearest neighbor communication to avoid long global wires.
Architecture
The first generation AsAP processor contains 36 identical processors with independant clock domains. Each processor is a reduced complexity programmable DSP with small memories, which can dramatically increase system area efficiency and energy efficiency. Each processor can receive data from any two neighbors and send data to any of its four neighbors. [1]
