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Bus Encoding is one of the popular techniques used in system design to reduce dynamic power consumed by the system bus.[1][2] Bus encoding aims to reduce the hamming distance between 2 consecutive values on the bus. Since the activity is directly proportional to the hamming distance, bus encoding proves to be effective in reducing the overall activity factor thereby reducing the dynamic power consumption in the system.

In the context of this article, a system can refer to anything where data is transferred from one element to another over bus (viz. System on a Chip (SoC), a computer system, an embedded system on board, etc.).

Motivation

The dynamic power dissipated by a CMOS circuit is directly proportional to the activity factor and the load capacitance as seen by the output of the CMOS gate. In case of a bus, the load capacitance is usually higher since bus needs to be connected to multiple modules and routed longer and the activity factor is also high. Due to higher value of load capacitance and activity factor, in a typical system, bus power consumption can contribute up to 50% of the total power consumption. Bus encoding aims to reduce this power by reducing the amount of activity (number of toggles) in the bus lines. While the kind of bus encoding to be used for a particular system can be best determined when the target application and environmental constraints about the system are known apriori, described below are some techniques which can help reduce bus power for most systems.

Examples of bus encoding

Following are some of the implementations to use Bus Encoding for reducing dynamic power consumption in different scenarios:

  1. Gray Encoding:[3] The address lines of a bus in most of the computing systems increase in consecutive numerical values due to spatial locality. If we use regular binary coding for the bus, we are not assured of minimal hamming distance between 2 consecutive addresses. Using gray codes for encoding the address lines will lead to a hamming distance of 1 between any 2 consecutive address bus values (as long as spatial locality holds). There are variations to this scheme named Shifted gray encoding to reduce the delay overhead.[4]
  2. Sequential addressing or T0 codes:[5] In case of address bus, due to spatial locality that exists in programs, most of the transitions involve changing the address to the next consecutive value. A possible encoding scheme is to use an additional line, INC, in the bus indicating whether the current transition is the next increment address or not. If it is not a consecutive address, then the receiver can use the value on the bus. But if it is a consecutive address, the transmitter need not change the value in the bus, but just assert the INC line to 1. In such case, for a continuous addressing scheme, there is no transition at all on the bus, leading to a bus activity factor of 0.
  3. Number representation: Let us consider an example of a system which gets one of its data from a sensor. Most of the times, the sensor may be measuring some noise and for this example, let us consider that the values being measured are (0) and (-1) alternatively. For a 32-bit data bus, value 0 translates to 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) while (-1) translates to 0xFFFFFFFF (1111 1111 1111 1111 1111 1111 1111 1111) in a 2’s complement representation. We see that the hamming distance in this case is 32 (since all 32-bits are changing their state). Instead, if we encode the bus to use signed integer representation (MSB is sign bit), we can represent 0 as 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) and -1 as 0x80000001 (1000 0000 0000 0000 0000 0000 0000 0001) . In this case, we see that the hamming distance between the numbers is just 2. Hence by using a 2’s complement to signed arithmetic encoding, we are able to reduce the activity from a factor of 32 to 2.
  4. Inversion Coding:[6][7] This is another implementation of bus encoding where an additional line named INV is added to the bus lines. Depending on the value of the INV line, the other lines will be used with or without inversion. e.g. if INV line is 0, the data on the bus is sampled as it is but if INV line is 1, the data on the bus is inverted before any processing on it. Referring to the example used in 3, instead of using a signed integer representation, we could continue using 2’s complement and achieve the same activity reduction using inversion encoding. 0 will be represented as 0x00000000 with INV=0. -1 will be represented as 0x00000000 with INV=1. Since INV=1, receiver will invert the data before consuming it, thereby converting it to 0xFFFFFFFF internally. In this case, only 1 bit (INV bit) is changed over bus leading to an activity of factor 1. In general, in inversion encoding, the encoder computes the hamming distance between the current value and next value and based on that, determines whether to use INV=0 or INV=1.
  5. Other techniques like Sector Based Encoding,[8] variations of Inversion coding, have also been proposed. There has been work on using bus encodings which lower the leakage power consumption as well along with reducing the crosstalk with minimal impact on path delays.[9][10]

Implementation Method

In case of SoC designs, bus encoding schemes can be best implemented in RTL by instantiating dedicated encoders and decoders over the bus. For some of the cases, it could be achieved by passing some directives to the synthesis tool either as a trace of the simulation[11] or by using synthesis pragma to define the type of encoding needed.

On board, a small low power IC can be deployed in between the master and slave modules on the bus to implement the encoding and decoding functions.

Property of the encoding function

The bus encoding/decoding function must be a Bijection which essestially mean two critical points:[3]

  1. Every data to be launched on the bus must have a unique encoded value and every encoded value must uniquely decode to the same original value.
  2. It must be possible to encode and decode all the values which can be generated by the source.

Trade-off/ Analysis

  • While adding of bus encoding reduces the activity factor over the bus and leads to reduction in dynamic power, addition of encoders and decoders around the bus causes additional circuitry to be added, which also consume some amount of dynamic power. We must factor this while computing the power savings.
  • The leakage power is increased due to the addition of gates. If the base activity factor of the system bus is not very high, bus encoding may not be a very viable option since it will degrade overall energy consumption due to leakage power.
  • If the bus timing is in the critical data path, adding of additional circuitry in the path will degrade the timing path and may prove detrimental. This analysis needs to be done carefully to determine what kind of bus encoding to use.

See also

References

  1. ^ M. Pedram and A Abdollahi, “Low Power RT-Level Synthesis Techniques: A Tutorial”
  2. ^ Devadas & Malik, “A Survey of Optimization Techniques targeting Low Power VLSI Circuits”, DAC 32, 1995, pp. 242-247
  3. ^ a b Wei-Chung Cheng and Massoud Pedram "Memory Bus Encoding for Low Power: A Tutorial"
  4. ^ http://www.sciencedirect.com/science/article/pii/S1383762110000159
  5. ^ L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems,” Proc. Seventh Great Lakes Symposium on VLSI, pp. 77-82, Mar.1997.
  6. ^ M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,” IEEE Transactions On VLSI Systems, Vol.3, No.1, pp.49-58, 1995
  7. ^ http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt
  8. ^ http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf
  9. ^ H. Deogun, R. R. Rao, D. Sylvester, and D. Blaauw. Leakage-and crosstalk-aware bus encoding for total power reduction. In Proceedings of the 41st Design Automation Conference, pages 779–782, June 2004.
  10. ^ Z. Khan, T. Arslan, and A. Erdogan. A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems. In Proceedings of the 18th International Conference on VLSI Design , pages 751–756. IEEE Computer Society, January 2005.
  11. ^ http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf
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