Time-triggered architecture
A Time-Triggered system (or 'TT system') is a computer system that executes one or more sets of tasks according to a pre-determined task schedule.[1] Implementation of a TT system will typically involve use of a single interrupt that is linked to the periodic overflow of a timer. This interrupt may drive a task scheduler (a simple form of "operating system"). The scheduler will – in turn – release the system tasks at predetermined points in time.[1]
Alternatives
TT can be viewed as a subset of a more general event-triggered (ET) system architecture. Implementation of an ET system will typically involve use of multiple interrupts, each associated with specific periodic events (such as timer overflows) or aperiodic events (such as the arrival of messages over a communication bus at random points in time). ET designs are traditionally associated with the use of what is known as a real-time operating system (or RTOS), though use of such a software platform is not a defining characteristic of an ET architecture.[1]
History and Development
TT systems have been used for many years to develop safety-critical aerospace and related systems[2] Use of TT systems was popularised by the publication of "Patterns for Time-Triggered Embedded Systems" (PTTES) in 2001[1] and the related introductory book "Embedded C" in 2002.[3] The PTTES book also introduced the concepts of time-triggered hybrid schedulers (an architecture for time-triggered systems that require task pre-emption) and shared-clock schedulers (an architecture for distributed time-triggered systems involving multiple, synchronised, nodes).[1]
Since publication of PTTES, extensive research work on TT systems has been carried out.[4][5][6][7][8][9]
See also
- Event-driven programming (An alternative architecture for computer systems)
- IEC 61508 (A related safety standard)
- ISO 26262 (A related safety standard)
- DO-178C (A related safety standard)
References
- ^ a b c d e Pont, M.J. (2001) "Patterns for Time-Triggered Embedded Systems", Addison-Wesley / ACM Press. ISBN: 0-201-331381.
- ^ Ward, N. J. (1991) “The static analysis of a safety-critical avionics control system”, in Corbyn, D.E. and Bray, N. P. (Eds.) “Air Transport Safety: Proceedings of the Safety and Reliability Society Spring Conference, 1991” Published by SaRS, Ltd.
- ^ Pont, M.J. (2002) “Embedded C”, Addison-Wesley. ISBN: 0-201-79523-X.
- ^ Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) “Deploying a time-triggered shared-clock architecture in a multiprocessor system-on-chip design”, in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).
- ^ Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2007) “Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems”, Microprocessors and Microsystems, 31(5): 326-334.
- ^ Chan, K.L. and Pont, M.J. (2010) “Real-time non-invasive detection of timing-constraint violations in time-triggered embedded systems”, Proceedings of the 7th IEEE International Conference on Embedded Software and Systems, Bradford, UK, 2010, pp.1978-1986. Published by IEEE Computer Society. ISBN 978-0-7695-4108-2.
- ^ Gendy, A.K. and Pont, M.J. (2008) “Automatically configuring time-triggered schedulers for use with resource-constrained, single-processor embedded systems”, IEEE Transactions on Industrial Informatics, 4(1): 37-46.
- ^ Hughes, Z.M. and Pont, M.J. (2008) “Reducing the impact of task overruns in resource-constrained embedded systems in which a time-triggered software architecture is employed”, Transactions of the Institute of Measurement and Control, Vol. 30: pp.427-450.
- ^ Phatrapornnant, T. and Pont, M.J. (2006) “Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling”, IEEE Transactions on Computers, 55(2): 113-124.