Jump to content

Serial concatenated convolutional codes

From Wikipedia, the free encyclopedia
This is an old revision of this page, as edited by Dodger67 (talk | contribs) at 12:59, 5 May 2014 (Serial Concatenated Convolutional Codes: The lead never gets a heading). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.


Serial concatenated convolutional codes (SCCC) were analyzed in the 1990's in a series of publications from NASA's Jet Propulsion Laboratories (JPL). This research yielded a form of turbo-like serial concatenated codes that 1) were iteratively ('turbo') decodable with reasonable complexity, and 2) gave error correction performance comparable with the turbo codes. The analysis of SCCC's was spawned in part by the earlier discovery of turbo codes in 1993.

SCCC's typically include an inner code, an outer code, and a linking interleaver. A distinguishing feature of SCCC's is the use of a recursive convolutional code as the inner code. The recursive inner code provides the 'interleaver gain' for the SCCC, which is the source of the excellent performance of these codes.

Prior forms of serial concatenated codes typically did not use recursive inner codes. Additionally, the constituent codes used in prior forms of serial concatenated codes were generally too complex for reasonable soft-in-soft-out (SISO) decoding. SISO decoding is considered essential for turbo decoding.

Serial concatenated convolutional codes have not found wide spread commercial use, although they were proposed for communications standards such as DVB-S2. Nonetheless, the analysis of SCCC's has provided insight into the performance and bounds of all types of iterative decodable codes including turbo codes and LDPC codes.

US patent 6,023,783 covers some forms of SCCC's. This patent will expire on May 15, 2016.[1]

History

Serial concatenated convolutional codes were first analyzed view a view toward turbo decoding in "Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding" by S. Benedetto, D. Divsalar], G. Montorsi and F. Pollara.[2] This analysis yielded a set of observations for designing high performance, turbo decodable serial concatenated codes that resembled turbo codes. One of these observations was that the "the use of a recursive convolutional inner encoder always yields an interleaver gain." This is in contrast to the use of block codes or non-recursive convolutional codes, which do not provide comparable interleaver gain.

Additional analysis of SCCC's was done in "Coding Theorems for 'Turbo-Like' Codes" by D. Divsalar, Hui Jin, and Robert J. McEliece.[3] This paper analyzed repeat-accumulate (RA) codes which are the serial concatenation of an inner two-state recursive convolutional code (also called an 'accumulator' or parity-check code) with a simple repeat code as the outer code, with both codes linked by an interleaver. The performance of the RA codes is quite good considering the simplicity of the constituent codes themselves.

SCCC codes were further analyzed in "Serial Turbo Trellis Coded Modulation with Rate-1 Inner Code".[4] In this paper SCCC's were designed for use with higher order modulation schemes. Excellent performing codes with inner and outer constituent convolutional codes of only two or four states were presented.

Example Encoder

Fig 1 is an example of a SCCC.

Fig. 1. SCCC Encoder


The example encoder is comprised of a 16-state outer convolutional code and a 2-state inner convolutional code linked by an interleaver. The natural code rate of the configuration shown is 1/4, however, the inner and/or outer codes may be punctured to achieve higher codes rates as needed. For example, an overall code rate of 1/2 may be achieved by puncturing the outer convolutional code to rate 3/4 and the inner convolutional code to rate 2/3.

A recursive inner convolutional code is preferable for turbo decoding of the SCCC. The inner code may be punctured to a rate as high as 1/1 with reasonable performance.

Example Decoder

An example of an interative SCCC decoder.

Fig. 2. SCCC Decoder

The SCCC decoder includes two soft-in-soft-out (SISO) decoders and an interleaver. While shown as separate units, the two SISO decoders may share all or part of their circuitry. The SISO decoding may be done is serial or parallel fashion, or some combination thereof. The SISO decoding is typically done using Maximum a posteriori (MAP) decoders using the BCJR algorithm.

RSC Codes

Img. 3. Two-state recursive systematic convolutional (RSC) code. Also called an 'accumulator.' Useful for LDPC codes and inner constituent code for serial concatenated convolutional codes (SCCC's).
Img. 4. Four-state RSC code. Useful for SCCC's.
Img. 5. Sixteen-state RSC code. Useful for low error rate turbo codes for applications such as satellite links. Suitable as outer code for SCCC's.

Performance

SCCC's provide performance comparable to other iteratively decodable codes including turbo codes and LDPC codes. They are noted for having slightly worse performance at lower SNR environments (i.e. worse waterfall region), but slightly better performance at higher SNR environments (i.e. lower error floor).

See also

References

"Concatenated codes", Scholarpedia

"Concatenated Convolutional Codes and Iterative Decoding", Willian E. Ryan

Serial Concatenated Convolutional Codes