Serial concatenated convolutional codes

Comment: Illustrations or diagrams are not connected. The Ukulele Dude - Aggie80 (talk) 20:52, 3 April 2014 (UTC)

Serial Concatenated Convolutional Codes

Serial concatenated convolutional codes (SCCC) were analyzed in the 1990's in a series of publications from NASA's Jet Propulsion Laboratories (JPL). This research yielded a form of turbo-like serial concatenated codes that 1) were iteratively ('turbo') decodable with reasonable complexity, and 2) gave error correction performance comparable with the turbo codes. The analysis of SCCC's was spawned in part by the earlier discovery of turbo codes in 1993.

SCCC's typically include an inner code, an outer code, and a linking interleaver. A distinguishing feature of SCCC's is the use of a recursive convolutional code as the inner code. The recursive inner code provides the 'interleaver gain' for the SCCC, which is the source of the excellent performance of these codes.

Prior forms of serial concatenated codes typically did not use recursive inner codes. Additionally, the constituent codes used in prior forms of serial concatenated codes were generally too complex for reasonable soft-in-soft-out (SISO) decoding. SISO decoding is considered essential for turbo decoding.

Serial concatenated convolutional codes have not found wide spread commercial use, although they were proposed for communications standards such as DVB-S2. Nonetheless, the analysis of SCCC's has provided insight into the performance and bounds of all types of iterative decodable codes including turbo codes and LDPC codes.

US patent 6,023,783 covers some forms of SCCC's. This patent will expire on May 15, 2016.

History

Serial concatenated convolutional codes were first analyzed view a view toward turbo decoding in "Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding"^[1] by S. Benedetto, D. Divsalar, G. Montorsi and F. Pollara. This analysis yielded a set of observations for designing high performance, turbo decodable serial concatenated codes that resembled turbo codes. One of these observations was that the "the use of a recursive convolutional inner encoder always yields an interleaver gain." This is in contrast to the use of block codes or non-recursive convolutional codes, which do not provide comparable interleaver gain.

Additional analysis of SCCC's was done in "Coding Theorems for 'Turbo-Like' Codes"^[2] by D. Divsalar, Hui Jin, and Robert J. McEliece. This paper analyzed repeat-accumulate (RA) codes which are the serial concatenation of an inner two-state recursive convolutional code (also called an 'accumulator' or parity-check code) with a simple repeat code as the outer code, with both codes linked by an interleaver. The performance of the RA codes is quite good considering the simplicity of the constituent codes themselves.

SCCC codes were further analyzed in "Serial Turbo Trellis Coded Modulation with Rate-1 Inner Code".^[3] In this paper SCCC's were designed for use with higher order modulation schemes. Excellent performing codes with inner and outer constituent convolutional codes of only two or four states were presented.

Example Encoder

Fig 1 is an example of a SCCC.

The example encoder is comprised of a 16-state outer convolutional code and a 2-state inner convolutional code linked by an interleaver. The natural code rate of the configuration shown is 1/4, however, the inner and/or outer codes may be punctured to achieve higher codes rates as needed. For example, an overall code rate of 1/2 may be achieved by puncturing the outer convolutional code to rate 3/4 and the inner convolutional code to rate 2/3.

A recursive inner convolutional code is preferable for turbo decoding of the SCCC. The inner code may be punctured to a rate as high as 1/1 with reasonable performance.

Example Decoder

An example of an interative SCCC decoder.

The SCCC decoder includes two soft-in-soft-out (SISO) decoders and an interleaver. While shown as separate units, the two SISO decoders may share all or part of their circuitry. The SISO decoding may be done is serial or parallel fashion, or some combination thereof. The SISO decoding is typically done using Maximum a posteriori (MAP) decoders using the BCJR algorithm.

LDPC Encoder

Figure X provides an illustration of the functional components of most LDPC encoders.

During the encoding of a frame, the input data bits (D) are repeated and distributed to a set of constituent encoders. The constituent encoders are typically accumulators and each accumulator is used to generate a parity symbol. A single copy of the original data D is transmitted (S) with the parity bits (P) to make up the code symbols. The S bits from each constituent encoder are discarded.

In some cases a parity bit is encoded by a second constituent code (serial concatenation), but more typically all or most of the constituent encoding for the LDPC is done in parallel.

In an example using the DVB-S2 rate 2/3 code the encoded block size is 64800 symbols (N=64800) with 42300 data bits (K=43200) and 21600 parity bits ( M=21600). Each constituent code (check node) encodes 16 data bits except for the first party bit which encodes 8 data bits. The first 4680 data bits are repeated 13 times (used in 13 parity codes), while the remaining data bits are used in 3 parity codes (irregular LDPC code).

To compare, classic turbo codes typically use two convolutional codes of moderate depth (v=3 or 4) configured in parallel, each of which encodes the entire input block (K) of data bits. These constituent encoders are combined with a code interleaver which interleaves one copy of the frame to generate the parity symbols.

The LDPC, in contrast, uses many low depth (v=1) 'convolutional codes' (accumulators) in parallel, each of which encode only a small portion of the input frame. The many constituent codes are connected via the repeat and distribute operation which performs the function of the interleaver in the turbo code.

The ability to more precisely manage the connections of the various constituent codes and the level of redundancy for each input bit give more flexibility in the design of LDPC codes, which can lead to slightly better performance than turbo codes in some instances. Turbo Codes still seem to perform better than LDPCs at low code rates, or at least the design of good performing low rate codes is easier for Turbo Codes.

As a practical matter, the hardware that forms the accumulators is reused during the encoding process. That is, once a first set of party bits are generated and the parity bits stored, the same accumulator hardware is used to generate a next set of parity bits.

Performance

SCCC's provide performance comparable to other iteratively decodable codes including turbo codes and LDPC codes. They are noted for having slightly worse performance at lower SNR environments (i.e. worse waterfall region), but slightly better performance at higher SNR environments (i.e. lower error floor).

References

External links

"Concatenated codes", Scholarpedia

"Concatenated Convolutional Codes and Iterative Decoding", Willian E. Ryan