Jump to content

Serial concatenated convolutional codes

Add links
From Wikipedia, the free encyclopedia
This is an old revision of this page, as edited by Mrcodeguy (talk | contribs) at 21:45, 17 April 2014. The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.


Serial Concatenated Convolutional Codes

Serial concatenated convolutional codes (SCCC) were analyzed in the 1990's in a series of publications from NASA's Jet Propulsion Laboratories (JPL). This research yielded a form of turbo-like serial concatenated codes that 1) were iteratively ('turbo') decodable with reasonable complexity, and 2) gave error correction performance comparable with the turbo codes. The analysis of SCCC's was spawned in part by the earlier discovery of turbo codes in 1993.

SCCC's typically include an inner code, an outer code, and a linking interleaver. A distinguishing feature of SCCC's is the use of a recursive convolutional code as the inner code. The recursive inner code provides the 'interleaver gain' for the SCCC, which is the source of the excellent performance of these codes.

Prior forms of serial concatenated codes typically did not use recursive inner codes. Additionally, the constituent codes used in prior forms of serial concatenated codes were generally too complex for reasonable soft-in-soft-out (SISO) decoding. SISO decoding is considered essential for turbo decoding.

Serial concatenated convolutional codes have not found wide spread commercial use, although they were proposed for communications standards such as DVB-S2. Nonetheless, the analysis of SCCC's has provided insight into the performance and bounds of all types of iterative decodable codes including turbo codes and LDPC codes.

US patent 6,023,783 covers some forms of SCCC's. This patent will expire on May 15, 2016.

History

Serial concatenated convolutional codes were first analyzed view a view toward turbo decoding in "Serial Concatenation of Interleaved Codes: Performance Analysis, Design, and Iterative Decoding"[1] by S. Benedetto, D. Divsalar, G. Montorsi and F. Pollara. This analysis yielded a set of observations for designing high performance, turbo decodable serial concatenated codes that resembled turbo codes. One of these observations was that the "the use of a recursive convolutional inner encoder always yields an interleaver gain." This is in contrast to the use of block codes or non-recursive convolutional codes, which do not provide comparable interleaver gain.

Additional analysis of SCCC's was done in "Coding Theorems for 'Turbo-Like' Codes"[2] by D. Divsalar, Hui Jin, and Robert J. McEliece. This paper analyzed repeat-accumulate (RA) codes which are the serial concatenation of an inner two-state recursive convolutional code (also called an 'accumulator' or parity-check code) with a simple repeat code as the outer code, with both codes linked by an interleaver. The performance of the RA codes is quite good considering the simplicity of the constituent codes themselves.

SCCC codes were further analyzed in "Serial Turbo Trellis Coded Modulation with Rate-1 Inner Code".[3] In this paper SCCC's were designed for use with higher order modulation schemes. Excellent performing codes with inner and outer constituent convolutional codes of only two or four states were presented.

Example Encoder

Fig 1 is an example of a SCCC.

Fig. 1. SCCC Encoder


The example encoder is comprised of a 16-state outer convolutional code and a 2-state inner convolutional code linked by an interleaver. The natural code rate of the configuration shown is 1/4, however, the inner and/or outer codes may be punctured to achieve higher codes rates as needed. For example, an overall code rate of 1/2 may be achieved by puncturing the outer convolutional code to rate 3/4 and the inner convolutional code to rate 2/3.

A recursive inner convolutional code is preferable for turbo decoding of the SCCC. The inner code may be punctured to a rate as high as 1/1 with reasonable performance.

Example Decoder

An example of an interative SCCC decoder.

Fig. 2. SCCC Decoder

The SCCC decoder includes two soft-in-soft-out (SISO) decoders and an interleaver. While shown as separate units, the two SISO decoders may share all or part of their circuitry. The SISO decoding may be done is serial or parallel fashion, or some combination thereof. The SISO decoding is typically done using Maximum a posteriori (MAP) decoders using the BCJR algorithm.


LDPC Encoder

Since LDPC are typically described by using a parity (H) matrix rather than the Generator (G) Matrix the actual encoding process is often not entirely clear. For most well designed LDPC codes the process is rather simple and involves the use of accumulators to generate each parity bit.

Figure X provides an illustration of the functional components of most LDPC encoders.

Fig. 1. LDPC Encoder

The code is a K/N LDPC code with M party bits, where M = N-K. The data bits to be encoded are D0-DK-1. These data bits are repeated and distributed to the set of accumulator according to the generator matrix G. The number of repeats represents the number of codes (checks) that use the data bit.

The number of repeats for each data bit D may be the same (regular LDPC code) or slightly different (irregular LDPC code). Irregular LDPC have been shown to give better performance so they are more common.

In general the number of repeats is going to be very low for each data bit; a data bit is typically used in only 3-8 codes.

For example, DVB-S2 rate 2/3 code has N=64800 (block size) with K=43200 (42300 data bits) and M=21600 (21600 parity bits). All but one parity code uses 16 data bits. A subset of 4680 data bits are used in 13 parity codes while the remaining data bits are used in 3 parity codes.

In some LDPC codes the parity symbols may be fed back for use in other check codes, which is essentially a serial concatenation of two codes. However, most LDPC codes are implemented using all or the vast majority of check codes configured in parallel rather than serial.

This parallel configuration lends itself to comparison with classic turbo codes, which use two convolutional codes (typically of higher depth) configured in parallel in combination with a code interleaver to generate the parity symbols.

If the accumulators are viewed as two-state convolutional codes, the LDPC resembles a turbo code that substitutes many lower depth (and shorter) codes in parallel for the two higher depth constituent convolutional codes of the classic turbo codes. Additionally, the interleaver is replaced by the repetition and distribution function of the LDPC encoder.

This is in contrast to serial concatenated codes, including serial concatenated convolutional codes (SCCC), which use many or all of the parity bits generated by some codes as the input to other codes (and also may involve the use of an interleaver).

Performance

SCCC's provide performance comparable to other iteratively decodable codes including turbo codes and LDPC codes. They are noted for having slightly worse performance at lower SNR environments (i.e. worse waterfall region), but slightly better performance at higher SNR environments (i.e. lower error floor).

See also

References

  1. ^ http://www.systems.caltech.edu/EE/Courses/EE127/EE127C/handout/serial.pdf
  2. ^ http://www.mif.vu.lt/~skersys/vsd/turbo/Allerton98.pdf
  3. ^ http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/18647/1/99-2030.pdf

"Concatenated codes", Scholarpedia

"Concatenated Convolutional Codes and Iterative Decoding", Willian E. Ryan

Serial Concatenated Convolutional Codes

Retrieved from "https://en.wikipedia.org/w/index.php?title=Serial_concatenated_convolutional_codes&oldid=604651563"