Simple Bus Architecture

SBA Master code example

SBA Master IP Core Interface

SBA Slave IP Core Interface

SBA Address Space IP Core Interface

The Simple Bus Architecture (SBA) is a form of computer architecture, made up software tools and intellectual property cores (IP Core) interconnected by buses set through simple and clear rules, that allow the implementation of an embedded system (SoC); additionally, basic templates are provided to achieve a rapid design. Its structure gives it an inherent educative value. The VHDL code that implements this architecture is highly portable.

Master core

The master core is developed as a special module or state machine and has the ability to perform basic data flow and processing, similar to a microprocessor but without the high consumption of its logic resources. One possible way to implement finite state machines is to have a controller of some type which acts as switch box. When the thread of execution swings around to execute code of the FSM, it is pointed at the controller which evaluates or determines the current state, usually through the use of a switch (case) statement or if-then-else statements. Once the current state is determined, the code for that state is executed, actions performed and possibly state transitions for the next time the FSM is executed. The controller may be a simple switch statement evaluating an integer, but an implementation may see the controller performing some pre-processing of inputs and triggering of state transitions before-hand.

Wishbone

The SBA is an application and simplified version of the Wishbone specification. The SBA implements the minimum essential subset of Wishbone signals interface, and can be easily connected with simple Wishbone IP Cores. The SBA defines three types of cores: masters, slaves and auxiliaries. Several slaves IP Cores were developed following the SBA architecture, many of them to implement virtual instruments.