Machine Check Architecture
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In computing, Machine Check Architecture (MCA) refers to an Intel mechanism in which the CPU reports hardware errors to the operating system.
Intel's Pentium 4, Intel Xeon, P6 family processors as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.[1]
See also
- Machine Check Exception (MCE)
- High availability
- Processor Abstraction Layer
- System Abstraction Layer
- Reliability, availability and serviceability (computer hardware)
References
External links
- Intel 64 and IA-32 Architectures Software Developer's Manuals
- Microsoft's article on Itanium's MCA
- A short description of x86 MCA
- Linux x86 daemon for processing of machine checks
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