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Intel APIC Architecture

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The Intel APIC Architecture is a system of advanced programmable interrupt controllers (APICs) designed by Intel for use in symmetric multiprocessor (SMP) computer systems. It was originally implemented by the Intel 82093AA and 82489DX, and is found in most x86 SMP motherboards. It is one of several attempts to solve interrupt routing efficiency issues in multiprocessor computer systems.

Overview

There are two components in the Intel APIC system, the local APIC (LAPIC) and the I/O APIC. There is one LAPIC in each CPU in the system. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components.

In systems containing an 8259 PIC, the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), or to one of the system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time.

Local APICs

LAPICs manage all external interrupts for some specific processor in an SMP system. In addition, it is able to accept and generate inter-processor interrupts (IPIs) between LAPICs. LAPICs may support up to 224 usable interrupt vectors from an I/O APIC. Vectors numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.

All Intel processors starting with the P54C have built-in local APIC. In single-processor systems, the major advantage of the local APIC is that PCI cards no longer have to have their interrupts mapped to ISA interrupts, but can use virtual PCI IRQs above 15, resulting in fewer conflicts and better performance. In the Microsoft family of operating system, Windows XP was the first to properly make use of the local APIC for this purpose, with some partial support present in Windows 2000.[1] In Windows 2000, the spreading of PCI card interrupts to virtual IRQ happens only if the machine also has an I/O APIC. Microsoft blamed their Windows 2000 implementation on information they had received from Intel supposedly promising that all future systems would contain an I/O APIC as well, something that in retrospect did not happen.[2] The sudden widespread use of the local APIC with Windows XP did expose a number of bugs in various BIOS implementations. In particular, Microsoft was forced to retain the PCI IRQ stacking behavior for any machine with a CardBus controller (and without an I/O APIC).[2]

The Message Signaled Interrupts (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.[2] Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.[3]

I/O APICs

I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. The first generation I/O APIC, the 82093, had support for 24 interrupt lines.[3]

According to a 2009 Intel benchmark using Linux, the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.[4]

Problems

There are a number of known bugs in implementations of APIC systems, especially with concern to how the 8254 is connected. Defective BIOSes may not set up interrupt routing properly, or provide incorrect ACPI tables and Intel MultiProcessor Specification (MPS) tables. Finally, the APIC can also be a cause of system failure when the operating system does not support it properly. On older operating systems, people often had to disable the I/O and local APICs. While this is not possible anymore due to the prevalence of Symmetric multiprocessor and multi-core systems, the bugs in the firmware and the operating systems are now a rare occurrence.

More information

More information on the Intel APIC Architecture can be found in the Intel 64 and IA-32 Intel Architecture Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1, Chapter 10, freely available on the Intel website.

See also

References

  1. ^ Scott M. Mueller (2011). Upgrading and Repairing PCs (20th ed.). Que Publishing. p. 242. ISBN 978-0-13-268218-3.
  2. ^ a b c APIC-Based Interrupt Subsystems on Uniprocessor PCs
  3. ^ a b James Coleman, Reducing Interrupt Latency Through the Use of Message Signaled Interrupts, pp. 10-11
  4. ^ James Coleman, Reducing Interrupt Latency Through the Use of Message Signaled Interrupts, p. 19
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