Forte Design Systems
| Company type | Private |
|---|---|
| Founded | 1 January 2001  |
| Headquarters | San Jose, California, USA |
Key people |
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| Website | www |
Forte Design Systems, Inc. Forte is a provider of high-level synthesis (HLS) software products, also known as electronic system-level (ESL) synthesis or behavioral synthesis that enable design at a higher level of abstraction[clarification needed]. Forte's main product is Cynthesizer. It was announced on Feb. 5, 2014 that it had entered into an agreement to be acquired by Cadence Design Systems[1]. The acquisition is expected to close within 30 days. Terms of the transaction were not disclosed.
History
The company was founded in 1998 as C2 Design Automation by John Sanguinetti and a team of engineers. In 2000, it merged with Chronology (founded in 1990) to become Forte Design Systems. It was announced on Feb. 5, 2014 that it had entered into an agreement to be acquired by Cadence Design Systems.
Management team
- Sean Dart, President and Chief Executive Officer
- John Sanguinetti, CTO and Founder
- Brett Cline, VP of Marketing and Sales
- Mike Meredith, VP of Technical Marketing
Product
 | This section contains promotional content. (January 2010) |
Cynthesizer is a high-level synthesis product that allows design teams to create complex electronic systems using ASICs, FPGAs and SoCs from algorithmic designs. Cynthesizer takes high-level SystemC description and automatically creates Verilog RTL code. Designers can use Cynthesizer to automatically build designs with custom interfaces and architectural requirements, retarget designs to new speeds and process technologies without code changes and supports derivative designs and reuse.
Forte and other companies in this space struggle with SystemC being an accepted standard for using C++ for designs, while SystemC is not actually very good for that (or anything really). C as a design language is equally bad since neither have any ability to natively represent the parallelism present in hardware systems. As such the use of C++ in design of hardware does nothing to reduce the complexity over (say) VHDL or SystemVerilog, and the hype has yet to match the reality.
References
- ^ Cadence press release: Cadence to Enhance High-Level Synthesis Offering with Acquisition of Forte Design Systems
- "Hardware design and levels of abstraction", EETimes 2007.
- "Forte Design Systems' Forte", EDA Café 2006.
- "Got system-level synthesis?", EEDesign 2005.