Simple Bus Architecture
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The Simple Bus Architecture[1] (SBA) is an architecture made up software tools and intellectual property cores (IP Core) interconnected by buses set through simple and clear rules, that allow the implementation of a embedded system (SoC); additionally, basic templates are provided to achieve a rapid design. Its structure gives it an inherent educative value. The VHDL code that implements this architecture is highly portable.
Master core
The master core developed as a special state machine has the ability to perform basic data flow and processing, similar to a microprocessor but without the high consumption of its logic resources.
Wishbone
The SBA is an application and simplified version of the Wishbone,[2] specification. The SBA implements the minimum essential subset of Wishbone signals interface, and can be easily connected with simple Wishbone IP Cores. The SBA defines three types of cores: masters, slaves and auxiliaries. Several slaves IP Cores were developed following the SBA architecture, many of them to implement virtual instruments.
References
- ^ SBA Bus Architecture home page [online] http://sba.accesus.com
- ^ OpenCores. (2011) “Wishbone, Revision B.4 Specification.” [Online]. http://opencores.org/opencores,wishbone