Inter-processor interrupt

An inter-processor interrupt (IPI) is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system. IPIs are typically used to implement a cache coherency synchronization point.

Mechanism

The M65MP option of OS/360 used the Direct Control feature of the S/360 to generate an interrupt on another processor; MVS uses the SIGNAL PROCESSOR instruction of the S/370, which provided a more formalized interface.

On IBM PC compatible computers that use the Advanced Programmable Interrupt Controller (APIC), IPI signalling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.

Examples

Windows

In a Microsoft Windows based multiprocessor system, a processor may interrupt another processor for the following reasons:

1. Queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution.
2. Updating the processor's translation lookaside buffers cache.
3. System shutdown.
4. System crash.
5. Kernel debugger breakpoint.

IPIs are given an IRQL of 29.

Linux/Unix

In Unix/Linux, the IPI interrupt is often used by the CPU in the SMP and AMP configurations to communicate with other processors in the setup.

Other uses

In x86 based systems, an IPI synchronizes the cache and memory management unit (MMU) between processors.

See also

• Advanced Programmable Interrupt Controller (APIC)
• Interrupt
• Interrupt handler
• Non-maskable interrupt (NMI)
• Programmable Interrupt Controller (PIC)

External links

• Interrupts and Exceptions