X86 Bit manipulation instruction set

Bit Manipulation Instructions (BMI) sets are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD, The purpose of the instruction set is to improve the speed of bit manipulation. The instructions all operate on general purpose registers.

There are two sets published by Intel, BMI1 and BMI2 both introduced with Haswell architecture, and two by AMD, ABM (Advanced Bit Manipulation) which is also a subset of SSE4a, and implemented by Intel as part of SSE4.2 and BMI1, and TBM (Trailing Bit Manipulation) extension, not implemented by Intel yet.

ABM

ABM is only implemented as a single instruction set by AMD. Intel considers POPCNT part of SSE4.2 and LZCNT part of BMI1. Both instructions have separate CPUID flags.

Instruction	Description
POPCNT	Population count.
LZCNT	Count the Number of Leading Zero Bits .

BMI1

Instruction	Description
ANDN	Logical And Not.
BEXTR	Bit Field Extract (with register).
BLSI	Extract Lowest Set Isolated Bit.
BLSMASK	Get Mask Up to Lowest Set Bit.
BLSR	Reset Lowest Set Bit.
TZCNT	Count the Number of Trailing Zero Bits

BMI2

Instruction	Description
BZHI	Zero High Bits Starting with Specified Bit Position.
MULX	Unsigned Multiply.
PDEP	Parallel Bits Deposit.
PEXT	Parallel Bits Extract.
RORX	Rotate Right Logical.
SARX	Shift Arithmetic Right.
SHRX	Shift Logical Right.
SHLX	Shift Logical Left.

TBM

Instruction	Description
BEXTR	Bit Field Extract (with Immediate)
BLCFILL	Fill From Lowest Clear Bit.
BLCI	Isolate Lowest Clear Bit.
BLCIC	Isolate Lowest Clear Bit and Complement.
BLCMASK	Mask From Lowest Clear Bit.
BLCS	Set Lowest Clear Bit.
BLSFILL	Fill from Lowest Set Bit.
BLSIC	Isolate Lowest Set Bit and Complement.
T1MSKC	Inverse Mask from Trailing Ones.
T2MSK	Mask From Trailing Zeroes.

Supporting CPUs

• Intel
  • Intel Nehalem processors and newer. Supports POPCNT as part of SSE4.2.
  • Intel Haswell processors. Supports ABM, BMI1 and BMI2.
• AMD
  • AMD Barcelona-based processors. Supports ABM.
  • AMD Bulldozer-based processors. Supports ABM.
  • AMD Piledriver-based processors. Supports ABM, BMI1 and TBM.
  • AMD Steamroller-based processors. Supports ABM, BMI1 and TBM.
  • AMD Excavator-based processors. Supports ABM, BMI1, BMI2 and TBM.
  • AMD Bobcat-based processors. Supports ABM.
  • AMD Jaguar-based processors. Supports ABM and BMI1.

See also

• AES instruction set
• CLMUL instruction set
• FMA
• AVX